Candidate: Yongtao You
Advisor: Alan Siegel
TOWARD A FULLY INTEGRATED
VLSI CAD SYSTEM:
FROM CUSTOM TO FULLY AUTOMATIC
10:00 a.m., Friday, January 25, 1991
7th floor conference room, 715 Broadway
This thesis describes an integrated CAD environment, which is intented to support almost all phases of the VLSI circuit design cycle, from high-level circuit description down to mask specification. Several VLSI CAD tools have been integrated together under the environment, including a multi-level simulator Msim, a hardware description language CHDL, some automatic placement tools, a schematic layout editor, and the UC Berkeley-developed geometry layout editor Magic.
The multi-level simulator Msim supports top-down design by allowing circuits whose components are described at different levels to be simulated together. The levels of circuit description currently supported include a hardware description language CHDL, which is a variant of the C programming language for circuit behavior descriptions, a schematic layout representation, and the Magic layout from which masks for wafer fabrication can be generated.
The schematic layout editor allows designers to specify interconnections among circuit components in a very efficient manner. It supports both behavioral descriptions and high level geometric layout of a circuit. Designers can have a graphical view of their design, and specify, within this graphical organization, the behavioral description of components at different levels of abstraction. These schematic layouts with different levels of representation can be simulated using the multi-level simulator Msim.
The automatic placement tool presently performs bottom-up iterative improvement, with simulated annealing as its assistant when needed. An interactive graphics interface is provided which allows human intervention on intermediate as well as final layouts.
In addition, the linear (true) charge-sharing modeling problem with indeterminate transistor switches is shown to be NP-Complete, which explains why it is integrated exclusively within the lattice model for our switch-level simulation.