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Chapter 14 -- 80386 Real-Address Mode
prev: 14.4 Entering and Leaving Real-Address Mode
next: 14.6 Real-Address Mode Exceptions
14.5 Switching Back to Real-Address Mode
The processor reenters real-address mode if software clears the PE bit in
CR0 with a
MOV to CR0 instruction.
A procedure that attempts to do this,
however, should proceed as follows:
- If paging is enabled, perform the following sequence:
- Transfer control to linear addresses that have an identity mapping;
i.e., linear addresses equal physical addresses.
- Clear the PG bit in CR0.
- Move zeros to CR3 to clear out the paging cache.
- Transfer control to a segment that has a limit of 64K (FFFFH). This
loads the CS register with the limit it needs to have in real mode.
- Load segment registers SS, DS, ES, FS, and GS with a selector that
points to a descriptor containing the following values, which are
appropriate to real mode:
- Limit = 64K (FFFFH)
- Byte granular (G = 0)
- Expand up (E = 0)
- Writable (W = 1)
- Present (P = 1)
- Base = any value
- Disable interrupts. A
CLI instruction disables INTR interrupts. NMIs
can be disabled with external circuitry.
- Clear the PE bit.
- Jump to the real mode code to be executed using a far
JMP. This
action flushes the instruction queue and puts appropriate values in
the access rights of the CS register.
- Use the
LIDT
instruction to load the base and limit of the real-mode
interrupt vector table.
- Enable interrupts.
- Load the segment registers as needed by the real-mode code.
up:
Chapter 14 -- 80386 Real-Address Mode
prev: 14.4 Entering and Leaving Real-Address Mode
next: 14.6 Real-Address Mode Exceptions