14.5 Switching Back to Real-Address Mode

1. If paging is enabled, perform the following sequence:
   • Transfer control to linear addresses that have an identity mapping; i.e., linear addresses equal physical addresses.
   • Clear the PG bit in CR0.
   • Move zeros to CR3 to clear out the paging cache.
2. Transfer control to a segment that has a limit of 64K (FFFFH). This loads the CS register with the limit it needs to have in real mode.
3. Load segment registers SS, DS, ES, FS, and GS with a selector that points to a descriptor containing the following values, which are appropriate to real mode:
   • Limit = 64K (FFFFH)
   • Byte granular (G = 0)
   • Expand up (E = 0)
   • Writable (W = 1)
   • Present (P = 1)
   • Base = any value
4. Disable interrupts. A CLI instruction disables INTR interrupts. NMIs can be disabled with external circuitry.
5. Clear the PE bit.
6. Jump to the real mode code to be executed using a far JMP. This action flushes the instruction queue and puts appropriate values in the access rights of the CS register.
7. Use the LIDT instruction to load the base and limit of the real-mode interrupt vector table.
8. Enable interrupts.
9. Load the segment registers as needed by the real-mode code.

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