CS372H Spring 2011 Homework 2
Problem 1
Given the following program that uses
three
memory segments in an address space as described in class (code
segment,
data segment ,and stack segment):
char
a[100];
main(int
argc, char **
argv)
{
int
d;
staticdouble
b;
char *s
= "boo", * p;
p = malloc(300);
return
0;
}
Identify the segment in which each variable
resides
and indicate if the variable is private to the thread or is
shared among
threads.
Be careful.
Problem 2
True or false. A virtual memory system that uses paging is
vulnerable to external fragmentation.
Problem 3 (based on reading; not
covered in lecture)
Segmented memory schemes (as well as user-level memory allocators
like
malloc() and, later in class, some disk placement
schemes) use various policies for fitting variable sized allocation
units into variable-sized spaces. Concoct a scenario in which
Best-fit allocation
outperforms First-fit, Worst-fit, and Buddy allocation (see the book
for details on these algorithms). Repeat for First-fit v. the
others,
Worst-fit v. the others, and Buddy allocation v. the others.
Problem 4 (based on reading; not
covered in lecture)
Describe the data structures required to implement
best-fit memory allocation.
Problem 5
This question refers to an architecture using segmentation with
paging (you may need to consult the text for details).
In this architecture, the 32-bit virtual address is divided into
fields
as follows:
4 bit segment number |
12 bit page number |
16 bit offset |
Here are the relevant tables (all values in hexadecimal):
Segment Table | |
Page Table A | |
Page Table B |
0 | Page Table A | |
0 | CAFE | |
0 | F000 |
1 | Page Table B | |
1 | DEAD | |
1 | D8BF |
x | (rest invalid) | |
2 | BEEF | |
x | (rest invalid) |
| | |
3 | BA11 |
| | |
| | |
x | (rest invalid) |
| | |
Find the physical address corresponding to each of the
following
virtual addresses (answer "bad virtual address" if the
virtual address is invalid):
- 00000000
- 20022002
- 10015555
Problem 6
In a 32-bit machine we subdivide the virtual address
into 4 segments as follows:
We use a 3-level page table, such that the first
10-bit are for the first level and so on.
-
What is the page size in such a system?
-
What is the size of a page table for a process
that has 256K of memory starting at address 0?
-
What is the size of a page table for a process
that has a code segment of 48K starting at address 0x1000000, a data
segment
of 600K starting at address 0x80000000 and a stack segment of 64K
starting
at address 0xf0000000 and growing upward (like in the PA-RISC of
HP)?
Problem 7
A computer system has a 36-bit virtual address space with a page size of 8K,
and 4 bytes per page table entry.
-
How many pages are in the virtual address space?
-
What is the maximum size of addressable physical memory in this
system?
-
If the average process size is 8GB, would you use a one-level,
two-level, or
three-level page table? Why?
-
Compute the average size of a page table in question 3 above.
Problem 8
In a 32-bit machine we subdivide the virtual address into 4 pieces as follows:
8-bit 4-bit 8-bit 12-bit
We use a 3-level page table, such that the first 8 bits are for the first level
and so on. Physical addresses are 44 bits and there are 4 protection bits per
page.
-
What is the page size in such a system?
-
How much memory is consumed by the page
table and wasted by internal fragmentation for a process that has
64K of memory
starting at address 0?
-
How much memory is consumed by the page
table and wasted by internal fragmentation for a process that has a
code
segment of 48K starting at address 0x1000000, a data segment of 600K
starting
at address 0x80000000 and a stack segment of 64K starting at address
0xf0000000
and growing upward (towards higher addresses)?
Problem 9
In keeping with the RISC processor design philosophy of moving hardware
functionality to software, you see a proposal that processor designers
remove the MMU (memory management unit)
from the hardware. To replace the MMU, the proposal has
compilers generate what is known as position independent code (PIC). PIC
can be loaded and run at any adress without any relocation being performed.
Assuming that PIC code runs just as fast as the non-PIC code, what would be
the disadvantaqge of this scheme compared to the page MMU used on
modern microprocessors?
Problem 10
Describe the advantages of using a MMU that incorporates segmentation
and paging over ones that are either pure paging or pure segmentation.
Present your answer as separate lists of advantages over each of the
pure schemes.