HW7 Solutions

1.
    - The kernel's code and data has physical address range 0x40000--0x58000
    - The physical address of the kernel's stack is 0x7f000.
    - The virtual addresses are the same as the physical addresses, because
    for this range of the virtual address space, the kernel's page table
    uses the identity mapping.
    - PAGENUMBER(MEMSIZE_PHYSICAL)


2
2.1. Sometimes. If the page is not present, then a TLB miss and a
    page fault will happen at the same time. If the page is not writable
    but it is in the TLB, then a store to memory can cause a page fault but
    no TLB miss. (And if the page is present and the permissions are
    consistent with the requested operation, yet the VA,PA mapping is
    not in the TLB, then there will be a TLB miss but no page fault.)

2.2. Sometimes. If the page is not present, or the permission check
fails, then there will be a page fault on top of the TLB miss.

2.3. Sometimes. Similar answer to above. 

2.4. Always. PTE_P | PTE_U means user readable.

2.5. Sometimes. If PTE_W is set, then it is permissible, otherwise not.


3
3.1
    Five. One for code loading. Two for data page 0x200000, and two for
    data page 0x300000. Why does each data page generate two TLB misses?
    When virtual address 0x200000 (for example) is referenced, there is
    a TLB miss (because the page was not present in virtual memory and
    so would not be in the TLB); then, when the page actually swaps into
    memory and the instruction is retried, there is another TLB miss.
    See section 21.5 in the book for more details. 

3.2
    Two page faults

4. Lay out the allocated memory so that the last legitimately allocated
byte is on the last byte of the allocated page (this "wastes" the first
part of a page).  Mark the next virtual page (past the array) as "not
in use" (this does not cost physical memory). At that point, memory
references past the end of the array will generate page faults.