This homework contains practice for thinking about virtual memory, which you will need for both the exams and lab 4. So you should totally work through the problems carefully even though, as usual, we're not going to grade these strictly.
Scheduling
How can fairness and throughput be competing goals for a scheduler? Give an example where a fair scheduler makes bad use of the CPU and an example where a high-throughput scheduler is unfair.
Virtual memory: warmup
This question is borrowed from CS:APP3e [Computer Systems: A Programmer’s Perspective (Third Edition), by Randy Bryant and David R. O’Hallaron].
Complete the following table, filling in the missing entries and replacing each question mark with the appropriate integer. Use the following units: K = 210 (kilo), M = 220 (mega), G = 230 (giga), T = 240 (tera), P = 250 (peta), or E = 260 (exa).
| Number of virtual address bits | Number of virtual addresses | Largest possible virtual address |
|---|---|---|
| 4 | 16 | 16 − 1 = 15 |
| 8 | ____ | ____ |
| ____ | 2? = 64 K | ____ |
| ____ | ____ | 232 − 1 = ? G - 1 |
| ____ | 2? = 256 T | ____ |
| 64 | ____ | ____ |
Virtual memory: paging
This question is also borrowed from CS:APP3e.
Determine the number of page table entries (PTEs) that are needed for the following combinations of virtual address size (n-bit addresses) and page size (P bytes).
| n | P | Number of PTEs |
|---|---|---|
| 16 | 4K | ____ |
| 16 | 8K | ____ |
| 32 | 4K | ____ |
| 32 | 8K | ____ |
| 48 | 4K | ____ |
Virtual memory: address translation
This question is also borrowed from CS:APP3e, and lightly modified.
Given a 32-bit virtual address space and a 24-bit physical address, determine the number of bits in the VPN, PPN (your book, OSTEP, calls this PFN), and offset, for the following page sizes P:
| P | # of VPN bits | # of PPN bits | # of offset bits |
|---|---|---|---|
| 1 KB | ____ | ____ | ____ |
| 2 KB | ____ | ____ | ____ |
| 4 KB | ____ | ____ | ____ |
| 8 KB | ____ | ____ | ____ |
TLB, page faults
Assume that the assembly code below is executed after a context switch. Make the following additional assumptions:
- The TLB is flushed (emptied) after context switch.
- Suppose all data pages (in the example below: 0x200000, 0x300000) are stored on disk when instruction 0x500 is executing.
- There is no prefetching.
[context switch]
0x500 movq 0x200000, %rax # move data in address 0x200000 to register %rax
0x504 incq %rax, 1 # add one to %rax
0x508 movq %rax, 0x300000 # move register %rax to memory at address 0x300000Answer the following questions:
- How many TLB misses will happen, and for which pages?
- How many page faults will happen, and for which pages?
Handing in the homework
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