Computer Architecture

Start Lecture #12

Chapter 5: The Processor: Datapath and Control

Homework: Start Reading Chapter 5.

5.1: Introduction

We are going to build a basic MIPS processor.

Figure 5.1 redrawn below shows the main idea

Note that the instruction gives the three register numbers as well as an immediate value to be added.

• No instruction actually does all this.
• We have datapaths for all possibilities.
• Will see how we arrange for only certain datapaths to be used for each instruction type.
  • For example R type uses all three registers but not the immediate field.
  • The I type uses the immediate but only two registers.
• The memory address for a load or store is the sum of a register and an immediate.
• The data value to be stored comes from a register.
• Why are we doing arithmetic on the program counter?

5.2 Logic Design Convention

Done in appendix B.

5.3: Building a Datapath

Let's begin doing the pieces in more detail.

We draw buses in magenta (mostly 32 bits) and control lines in green.

Instruction fetch

We are ignoring branches and jumps for now.

The diagram on the right shows the main loop involving instruction fetch (i-fetch)

• How come no write line for the PC register?
  Ans: We write it every cycle.
• How come no write line for the instruction memory.
  Ans: We don't write it (of course somehow it is written).
• How come no control for the ALU?
  Ans: This one always adds.
• How come no clock lines.
  Ans: Lazy; they should be drawn.

R-type instructions

We did the register file in appendix B. Recall the following points made when discussing the appendix.

• The words Read and Write in the diagram are adjectives not verbs.
• The register file contains two read ports and one write port. We mentioned in the appendix that this was to support MIPS instructions that read two and write one register. Now that we have covered the basic MIPs instructions, we know that it is precisely the R-type instructions that have this requirement.
• The 3-bit control line sent to the ALU consists of Bnegate and Op.
• We learned that the RegWrite control line is asserted if the write register is to be written. We know that is always the case for R-type instructions.

The 32-bit bus with the instruction is divided into three 5-bit buses for each register number (plus other wires not shown).

Homework: What would happen if the RegWrite line had a stuck-at-0 fault (was always deasserted)? What would happen if the RegWrite line had a stuck-at-1 fault (was always asserted)?

load and store

The diagram on the right shows the structures used to implement load word and store word (lw and sw).

lw $r,disp($s):

1. Computes the effective address formed by adding the 16-bit immediate constant disp (displacement) to the contents of register $s.
2. Fetches the value in data memory at this address.
3. Inserts this value into register $r.

sw $r,disp($s):

1. Computes the same effective address as lw $r,disp($s).
2. Stores the contents of register $r into this address.

We have a 32-bit adder and more importantly have a 32-bit addend coming from the register file. Hence we need to extend the 16-bit immediate constant to 32 bits. That is we must replicate the HOB of the 16-bit immediate constant to produce an additional 16 HOBs all equal to the sign bit of the 16-bit immediate constant. This is called sign extending the constant.

What about the control lines?

• RegWrite is deasserted for sw and asserted for lw.
• MemWrite is asserted for sw and deasserted for lw.
• We don't need memread since our memory (unlike real memory) is the same as our registers.
• The ALU Operation is set to add for lw and sw.
• For now we just write down which control lines are asserted and deasserted. Later we will do the circuit to calculate the control lines from the instruction word.

Homework: What would happen if the RegWrite line had a stuck-at-0 fault (was always deasserted)?
What would happen if the RegWrite line had a stuck-at-1 fault (was always asserted)?
What would happen if the MemWrite line had a stuck-at-0 fault (was always deasserted)?
What would happen if the MemWrite line had a stuck-at-1 fault (was always asserted)?

The Diagram is Wrong (specifically, incomplete)

The diagram cheats a little for clarity.

• For lw we write register r (and read s)
• For sw we read register r (and read s)
• But we indicated that the same bits in the instruction always go to the same ports in the register file.
• We are mux deficient.
  Some of the time we want group A to go to the port; other times we want group B to go to the port.
  Solution: Always send group A toward the port; always send group B toward the port; use a mux to choose which group goes there.
• We will put in the muxes later.

Branch on equal (beq)

Compare two registers and branch if equal. Recall the following from appendix B, where we built the ALU, and from chapter 2, where we discussed beq.

• To check for equal we subtract and test for zero (our ALU does this).
• The target of the branch instruction
    beq $r,$s,disp
  is the sum of
  1. The program counter PC after it has been incremented, that is, the address of the next sequential instruction.
  2. The 16-bit immediate constant disp (treated as a signed number) left shifted 2 bits (because the constant represent words and the address is specified in bytes.
• The value of PC after the increment is available. We computed it in the basic instruction fetch datapath.
• Since the immediate constant is signed it must be sign extended. As mentioned previously this is just replicating the HOB.

The top alu labeled add is just an adder so does not need any control

The shift left 2 is not a shifter. It simply moves wires and includes two zero wires. We need a 32-bit version. Below is a 5 bit version.

Homework: What would happen if the RegWrite line had a stuck-at-0 fault (was always deasserted)? What would happen if the RegWrite line had a stuck-at-1 fault (was always asserted)?

5.4: A Simple Implementation Scheme

We will first put the pieces together and later figure out the control lines that are needed and how to set them. We are not now worried about speed.

We are assuming that the instruction memory and data memory are separate. So we are not permitting self modifying code. We are not showing how either memory is connected to the outside world (i.e., we are ignoring I/O).

We must use the same register file with all the pieces since when a load changes a register, a subsequent R-type instruction must see the change and when an R-type instruction makes a change, the lw/sw must see it (for loading or calculating the effective address, etc).

We could use separate ALUs for each type of instruction but we are not worried about speed so we will use the same ALU for all instruction types. We do have a separate adder for incrementing the PC.

Combining R-type and lw/sw

The problem is that some inputs can come from different sources.

1. For R-type instructions, both ALU operands are registers. For I-type instructions (lw/sw) the second operand is the (sign extended) immediate field.
2. For R-type instructions, the write data comes from the ALU. For lw it comes from the memory.
3. For R-type instructions, the write register comes from field rd, which is bits 15-11. For sw, the write register comes from field rt, which is bits 20-16.

We will deal with the first two now by using a mux for each. We will deal with the third shortly by (surprise) using a mux.

Including instruction fetch

This is quite easy

Finally, beq

We need to have an if stmt for PC (i.e., a mux)

Homework: Extend the datapath just constructed to support the addi instruction as well as the instructions already supported.

Homework: Extend the datapath just constructed to support a variation of the lw instruction where the effective address is computed by adding the contents of two registers (instead of using an immediate field). This new instruction would be an R-type. Continue to support all the instructions that the original datapath supported.

Homework: Can you support a hypothetical swap instruction that swaps the contents of two registers using the same building blocks that we have used to date?