Address translation

• Each memory reference turns into 2 memory references
  1. Reference the page table
  2. Reference central memory
• This would be a disaster!
• Hence the MMU caches page#-->frame# translations. This cache is kept near the processor and can be accessed rapidly.
• This cache is called a translation lookaside buffer (TLB) or translation buffer (TB).
• For the above example, after referencing virtual address 3372, there would be an entry in the TLB containing the mapping 3-->459.
• Hence a subsequent access to virtual address 3881 would be translated to physical address 459881 without a memory reference.

Choice of page size is discuss below.

Homework: 8.

4.3: Virtual Memory (meaning fetch on demand)

Idea is that a program can execute even if only the active portion of its address space is memory resident. That is, swap in and swap out portions of a program. In a crude sense this can be called ``automatic overlays''.

Advantages

• Can run a program larger than the total physical memory.
• Can increase the multiprogramming level since the total size of the active, i.e. loaded, programs (running + ready + blocked) can exceed the size of the physical memory.
• Since some portions of a program are rarely if ever used, it is an inefficient use of memory to have them loaded all the time. Fetch on demand will not load them if not used and will unload them during replacement if they are not used for a long time (hopefully).

4.3.1: Paging (meaning demand paging)

Fetch pages from disk to memory when they are referenced, with a hope of getting the most actively used pages in memory.

• Very common: dominates modern operating systems.
• Started by the Atlas system at Manchester University in the 60s (Fortheringham).
• Each PTE continues to have the frame number if the page is loaded.
• But what if the page is not loaded (exists only on disk)?
  • The PTE has a flag indicating if it is loaded (can think of the X in the diagram on the right as indicating that this flag is not set).
  • If not loaded, the location on disk could be kept in the PTE (not shown in the diagram). But normally it is not (discussed below).
  • When a reference is made to a non-loaded page (sometimes called a non-existent page, but that is a bad name), the system has a lot of work to do. We give more details below.
    1. Choose a free frame, if one exists.
    2. If not
       1. Choose a victim frame.
          • More later on how to choose a victim.
          • Called the replacement question
       2. Write victim back to disk if dirty,
       3. Update the victim PTE to show that it is not loaded and, perhaps, where on disk it has been put.
    3. Copy the referenced page from disk to the free frame.
    4. Update the PTE of the referenced page to show that it is loaded and give the frame number.
    5. Do the standard paging address translation (p#,off)-->(f#,off).
• Really not done quite this way
  • There is ``always'' a free frame because ...
  • There is a deamon active that checks the number of free frames and if this is too low, chooses victims and ``pages them out'' (writing them back to disk if dirty).
• Choice of page size is discussed below.

Homework: 12.

4.3.2: Page tables

A discussion of page tables is also appropriate for (non-demand) paging, but the issues are more acute with demand paging since the tables can be much larger. Why?

1. The total size of the active processes is no longer limited to the size of physical memory. Since the total size of the processes is greater, the total size of the page tables is greater and hence concerns over the size of the page table are more acute.
2. With demand paging an important question is the choice of a victim page to page out. Data in the page table can be useful in this choice.

We must be able access to the page table very quickly since it is needed for every memory access.

Unfortunate laws of hardware.

• Big and fast are essentially incompatible.
• Big and fast and low cost is hopeless.

So we can't just say, put the page table in fast processor registers, and let it be huge, and sell the system for $1500.

For now, put the (one-level) page table in main memory.

• Seems too slow since all memory references require two reference.
• TLB very helpful to reduce the average delay as mentioned above (discussed later in more detail).
• The page table might be too big.
  • Currently we are considering contiguous virtual addresses ranges (i.e. the virtual addresses have no holes).
  • Typically put the stack at one end of virtual address and the global (or static) data at the other end and let them grow towards each other.
  • The memory in between is unused.
  • This unused memory can be huge (in address range) and hence the page table will mostly contain unneeded PTEs.
• Works fine if the maximum virtual address size is small, which was once true (e.g., the PDP-11 of the 1970s) but is no longer the case.

Contents of a PTE

Each page has a corresponding page table entry (PTE). The information in a PTE is for use by the hardware. Information set by and used by the OS is normally kept in other OS tables. The page table format is determined by the hardware so access routines are not portable. The following fields are often present.

1. The valid bit. This tells if the page is currently loaded (i.e., is in a frame). If set, the frame pointer is valid. It is also called the presence or presence/absence bit. If a page is accessed with the valid bit zero, a page fault is generated by the hardware.
2. The frame number. This is the main reason for the table. It is needed for virtual to physical address translation.
3. The Modified bit. Indicates that some part of the page has been written since it was loaded. This is needed when the page is evicted so the OS can know that the page must be written back to disk.
4. The referenced bit. Indicates that some word in the page has been referenced. Used to select a victim: unreferenced pages make good victims by the locality property (discussed below).
5. Protection bits. For example one can mark text pages as execute only. This requires that boundaries between regions with different protection are on page boundaries. Normally many consecutive (in logical address) pages have the same protection so many page protection bits are redundant. Protection is more naturally done with segmentation.

Multilevel page tables (Not on 202 final exam)

Recall the previous diagram. Most of the virtual memory is the unused space between the data and stack regions. However, with demand paging this space does not waste real memory. But the single large page table does waste real memory.

The idea of multi-level page tables (a similar idea is used in Unix inode-based file systems) is to add a level of indirection and have a page table containing pointers to page tables.

• Imagine one big page table.
• Call it the second level page table and cut it into pieces each the size of a page.
  Note that you can get many PTEs in one page so you will have far fewer of these pages than PTEs
• Now construct a first level page table containing PTEs that point to these pages.
• This first level PT is small enough to store in memory.
• But since we still have the 2nd level PT, we have made the world bigger not smaller!
• Don't store in memory those 2nd level page tables all of whose PTEs refer to unused memory. That is use demand paging on the (second level) page table

• For a two level page table the virtual address is divided into three pieces

  +-----+-----+-------+
  | P#1 | P#2 | Offset|
  +-----+-----+-------+
  

• P#1 gives the index into the first level page table.
• Follow the pointer in the corresponding PTE to reach the frame containing the relevant 2nd level page table.
• P#2 gives the index into this 2nd level page table
• Follow the pointer in the corresponding PTE to reach the frame containing the (originally) requested frame.
• Offset gives the offset in this frame where the requested word is located.

Do an example on the board

The VAX used a 2-level page table structure, but with some wrinkles (see Tanenbaum for details).

Naturally, there is no need to stop at 2 levels. In fact the SPARC has 3 levels and the Motorola 68030 has 4 (and the number of bits of Virtual Address used for P#1, P#2, P#3, and P#4 can be varied).