The control for the datapath

We start with our last figure, which shows the data path and then add the missing mux and show how the instruction is broken down.

We need to set the muxes.

We need to generate the three ALU cntl lines: 1-bit Bnegate and 2-bit OP

    And     0 00
    Or      0 01
    Add     0 10
    Sub     1 10
    Set-LT  1 11

What information can we use to decide on the muxes and alu cntl lines?

The instruction!

• Opcode field (6 bits)
• For R-type the funct field (6 bits)

So no problem, just do a truth table.

• 12 inputs, 3 outputs (this is just for the three ALU control lines).
• 4096 rows, 15 columns, 60K entries
• HELP!

We will let the main control (to be done later) ``summarize'' the opcode for us. It will generate a 2-bit field ALUOp

    ALUOp   Action needed by ALU

    00      Addition (for load and store)
    01      Subtraction (for beq)
    10      Determined by funct field (R-type instruction)
    11      Not used

How many entries do we have now in the truth table?

opcode	ALUOp	operation	funct field	ALU action	ALU cntl
LW	00	load word	xxxxxx	add	010
SW	00	store word	xxxxxx	add	010
BEQ	01	branch equal	xxxxxx	subtract	110
R-type	10	add	100000	add	010
R-type	10	subtract	100010	subtract	110
R-type	10	AND	100100	and	000
R-type	10	OR	100101	or	001
R-type	10	SLT	101010	set on less than	111

• Instead of a 6-bit opcode we have a 2-bit summary.
• We still have a 6-bit function (funct) field (needed for R-type).
• So now we have 8 inputs (2+6) and 3 outputs.
• 256 rows, 11 columns; ~2800 entries.
• Certainly easy for automation ... but we will be clever.
• We only have 8 MIPS instructions that use the ALU (fig 5.15).
• The first two rows are the same
• When funct is used its two HOBs are 10 so are don't care
• ALUOp=11 impossible ==> 01 = X1 and 10 = 1X
• So we get

    ALUOp | Funct        ||  Bnegate:OP
    1 0   | 5 4 3 2 1 0  ||  B OP
    ------+--------------++------------
    0 0   | x x x x x x  ||  0 10
    x 1   | x x x x x x  ||  1 10
    1 x   | x x 0 0 0 0  ||  0 10
    1 x   | x x 0 0 1 0  ||  1 10
    1 x   | x x 0 1 0 0  ||  0 00
    1 x   | x x 0 1 0 1  ||  0 01
    1 x   | x x 1 0 1 0  ||  1 11
    

How would we implement this?

• A circuit for each of the three output bits.
• Must decide when each output bit is 1.
• We do this one output bit at a time.
  
  

• Those rows where its bit is 1, rows 2, 4, and 7.

  ALUOp | Funct      
  1 0   | 5 4 3 2 1 0
  ------+------------
  x 1   | x x x x x x
  1 x   | x x 0 0 1 0
  1 x   | x x 1 0 1 0
  

• Notice that, in the 5 rows with ALUOp=1x, F1=1 is enough to distinugish the two rows where Bnegate is asserted.
• This gives

  ALUOp | Funct       
  1 0   | 5 4 3 2 1 0 
  ------+-------------
  x 1   | x x x x x x 
  1 x   | x x x x 1 x 
  

• Hence Bnegate is ALUOp0 + (ALUOp1 F1)

When is OP0 asserted?

• Start with the rows where its bit is set.

  ALUOp | Funct      
  1 0   | 5 4 3 2 1 0
  ------+------------
  1 x   | x x 0 1 0 1
  1 x   | x x 1 0 1 0
  

• But again looking at all the rows where ALUOp=1x we see that the two rows where OP0 is asserted are characterized by just two Function bits

  ALUOp | Funct      
  1 0   | 5 4 3 2 1 0
  ------+------------
  1 x   | x x x x x 1
  1 x   | x x 1 x x x
  

• So OP0 is ALUOp1 F0 + ALUOp1 F3

• Again we begin with the rows where its bit is one

  ALUOp | Funct      
  1 0   | 5 4 3 2 1 0
  ------+------------
  0 0   | x x x x x x
  x 1   | x x x x x x
  1 x   | x x 0 0 0 0
  1 x   | x x 0 0 1 0
  1 x   | x x 1 0 1 0
  

• Again inspection of the 5 rows with ALUOp=1x yields one F bit that distinguishes when OP1 is asserted, namely F2=0

  ALUOp | Funct      
  1 0   | 5 4 3 2 1 0
  ------+------------
  0 0   | x x x x x x
  x 1   | x x x x x x
  1 x   | x x x 0 x x
  

• Since x 1 in the second row is really 0 1, rows 1 and 2 can be combined to give

  ALUOp | Funct      
  1 0   | 5 4 3 2 1 0
  ------+------------
  0 x   | x x x x x x
  1 x   | x x x 0 x x
  

• Now we can use the first row to enlarge the scope of the last row

  ALUOp | Funct      
  1 0   | 5 4 3 2 1 0
  ------+------------
  0 x   | x x x x x x
  x x   | x x x 0 x x
  

• So OP1 = NOT ALUOp1 + NOT F2

The circuit is then easy.

Now we need the main control.

• Setting the four muxes.
• Writing the registers.
• Writing the memory.
• Reading the memory (for technical reasons, would not be needed if the memory was built from registers).
• Calculating ALUOp.

So 9 bits.

The following figure shows where these occur.

They all are determined by the opcode

The MIPS instruction set is fairly regular. Most fields we need are always in the same place in the instruction.

• Opcode (called Op[5-0]) is always in 31-26
• Regs to be read always 25-21 and 20-16 (R-type, beq, store)
• Base reg for effective address always 25-21 (load store)
• Offset always 15-0
• Oops: Reg to be written EITHER 20-16 (load) OR 15-11 (R-type) MUX!!

MemRead:	Memory delivers the value stored at the specified addr
MemWrite:	Memory stores the specified value at the specified addr
ALUSrc:	Second ALU operand comes from (reg-file / sign-ext-immediate)
RegDst:	Number of reg to write comes from the (rt / rd) field
RegWrite:	Reg-file stores the specified value in the specified register
PCSrc:	New PC is Old PC+4 / Branch target
MemtoReg:	Value written in reg-file comes from (alu / mem)

We have seen the wiring before.

We are interested in four opcodes.

• R-type
• load
• store
• BEQ

Do a stage play

• Need ``volunteers''
  1. One for each of 4 muxes
  2. One for PC reg
  3. One for the register file
  4. One for the instruction memory
  5. One for the data memory
• I will play the control
• Let the PC initially be zero
• Let each register initially contain its number (e.g. R2=2)
• Let each data memory word initially contain 100 times its address
• Let the instruction memory contain (starting at zero)

  add r9,r5,r1 r9=r5+r1   0   5   1   9   0  32
  sub r9,r9,r6            0   9   6   9   0  34
  beq r9,r0,-8            4   9   0   <  -2   >
  slt r1,r9,r0            0   9   0   1   0  42
  lw  r1,102(r2)         35   2   1   <  100  >
  sw  r9,102(r2) 
  

• Go!