Lab 1: Simulating A 1-bit ALU

Hand out Lab 1, which is available in text (without the diagram), pdf, and postscript.

Chapter 1: Computer Abstractions and Technologies

Homework: READ chapter 1. Do 1.1 -- 1.26 (really one matching question)
Do 1.27 to 1.44 (another matching question),
1.45 (and do 10,000 RPM),
1.46, 1.50

Chapter 3: Instructions: Language of the Machine

Homework: Read sections 3.1 3.2 3.3

3.4 Representing instructions in the Computer (MIPS)

Register file

• We just learned how to build this
• 32 Registers each 32 bits
• Register 0 is always 0 when read and stores to register 0 are ignored

Homework: 3.2.

The fields of a MIPS instruction are quite consistent

    op    rs    rt    rd    shamt  funct   <-- name of field
    6     5     5     5      5      6      <-- number of bits

• op is the opcode
• rs,rt are source operands
• rd is destination
• shamt is the shift amount
• funct is used for op=0 to distinguish alu ops
  • alu is arithmetic and logic unit
  • add/sub/and/or/not etc.
• We will see there are other formats (but similar to this one).

R-type instruction (R for register)

Example: add $1,$2,$3

• R-type use the format above
• The example given has for its 6 fields 0--2--3--1--0--32
• op=0, alu op
• funct=32 specifies add
• reg1 <-- reg2 + reg3
• The regs can all be the same (doubles the value in the reg).
• Do sub by just changing the funct
• If the regs are the same for subtract, the instruction clears the register.

I-type (why I?)

    op    rs    rt   address
    6     5     5     16

• rs is a source reg.
• rt is the destination reg.

Examples: lw/sw $1,1000($2)

• $1 <-- Mem[$2+1000]
  $1 --> Mem[$2+1000]
• Transfers to/from memory, normally in words (32-bits)
  • But the machine is byte addressable!
  • Then how come have load/store word instead of byte?
    Ans: It has load/store byte as well, but we don't cover it.
  • What if the address is not a multiple of 4?
    Ans: An error (MIPS requires aligned accesses).
• machine format is: 35/43 $2 $1 1000

RISC-like properties of the MIPS architecture.

• All instructions are the same length (32 bits).
• Field sizes of R-type and I-type correspond.
• The type (R-type, I-type, etc.) is determined by the opcode.
• rs is the reference to memory for both load and store.
• These properties will prove helpful when we construct a MIPS processor.

Branching instruction

slt (set less-then)

• R-type
• reg3 <-- (if reg8 < reg2 then 1 else 0)
• Like other R-types: read 2nd and 3rd reg, write 1st

beq and bne (branch (not) equal)

• I-type
• if reg1=reg2 then go to the 124rd instruction after this one.
• if reg1!=reg2 then go to the 124rd instruction after this one.
• Why 124 not 123?
  Ans: We will see that the CPU adds 4 to the program counter (for the no branch case) and then adds (times 4) the third operand.
• Normally one writes a label for the third operand and the assembler calculates the offset needed.

blt (branch if less than)

• I-type
• if reg5 < reg8 then go to the 124rd instruction after this one.
• *** WRONG ***
• There is no blt instruction.
• Instead use

      stl $1,$5,$8
      bne $1,$0,123
  

ble (branch if less than or equal)

• There is no ``ble $5,$8,L'' instruction.
• There is also no ``sle $1,$5,$8'' set $1 if $5 less or equal $8.
• Note that $5<=$8 <==> NOT ($8<$5).
• Hence we test for $8<$5 and branch if false.

      stl $1,$8,$5
      beq $1,$0,L
  

bgt (branch if greater than)

• There is no ``bgt $5,$8,L'' instruction.
• There is also no ``sgt $1,$5,$8'' set $1 if $5 greater than $8.
• Note that $5>$8 <==> $8<$5.
• Hence we test for $8<$5 and branch if true.

      stl $1,$8,$5
      bne $1,$0,L
  

bge (branch if greater than or equal)

• There is no ``bge $5,$8,L'' instruction.
• There is also no ``sge $1,$5,$8'' set $1 if $5 greater or equal $8l
• Note that $5>=$8 <==> NOT ($5<$8)l
• Hence we test for $5<$8 and branch if false.

      stl $1,$5,$8
      beq $1,$0,L
  

Note: Please do not make the mistake of thinking that

    stl $1,$5,$8
    beq $1,$0,L

    stl $1,$8,$5
    bne $1,$0,L

It is not the case that the negation of X < Y is Y < X.

End of Note

Homework: 3.12

J-type instructions (J for jump)

        op   address
        6     26

j (jump)

Example: j 10000

• Jump to instruction (not byte) 10000.
• Branches are PC relative, jumps are absolute.
• J type
• Range is 2^26 words = 2^28 bytes = 1/4 GB

jr (jump register)

Example: jr $10

• Jump to the location in register 10.
• R type, but uses only one register.
• Will it use one of the source registers or the destination register?
  Ans: This will be obvious when we construct the processor.

jal (jump and link)

Example: jal 10000

• Jump to instruction 10000 and store the return address (the address of the instruction after the jal).
• Used for subroutine calls.
• J type.
• Return address is stored in register 31. By using a fixed register, jal avoids the need for a second register field and hence can have 26 bits for the instruction address (i.e., can be a J type).