Including instruction fetch

This is quite easy

Finally, beq

We need to have an ``if stmt'' for PC (i.e., a mux)

Homework:

• 5.5 and 5.8 (just datapaths not control)
• 5.9

The control for the datapath

We start with our last figure, which shows the data path and then add the missing mux and show how the instruction is broken down.

We need to set the muxes.

We need to generate the three ALU cntl lines: 1-bit Bnegate and 2-bit OP

    And     0 00
    Or      0 01
    Add     0 10
    Sub     1 10
    Set-LT  1 11

What information can we use to decide on the muxes and alu cntl lines?

The instruction!

• Opcode field (6 bits)
• For R-type the funct field (6 bits)

So no problem, just do a truth table.

• 12 inputs, 3 outputs (this is just for the three ALU control lines).
• 4096 rows, 15 columns, 60K entries
• HELP!

We will let the main control (to be done later) ``summarize'' the opcode for us. It will generate a 2-bit field ALUOp

    ALUOp   Action needed by ALU

    00      Addition (for load and store)
    01      Subtraction (for beq)
    10      Determined by funct field (R-type instruction)
    11      Not used

How many entries do we have now in the truth table?

• Instead of a 6-bit opcode we have a 2-bit summary.
• We still have a 6-bit function (funct) field (needed for R-type).
• So now we have 8 inputs (2+6) and 3 outputs.
• 256 rows, 11 columns; ~2800 entries.
• Certainly easy for automation ... but we will be clever.
• We only have 8 MIPS instructions that use the ALU (fig 5.15).

  opcode	ALUOp	operation	funct field	ALU action	ALU cntl
  LW	00	load word	xxxxxx	add	010
  SW	00	store word	xxxxxx	add	010
  BEQ	01	branch equal	xxxxxx	subtract	110
  R-type	10	add	100000	add	010
  R-type	10	subtract	100010	subtract	110
  R-type	10	AND	100100	and	000
  R-type	10	OR	100101	or	001
  R-type	10	SLT	101010	set on less than	111

• The first two rows are the same
• When funct is used its two HOBs are 10 so are don't care
• ALUOp=11 impossible ==> 01 = X1 and 10 = 1X
• So we get

    ALUOp | Funct        ||  Bnegate:OP
    1 0   | 5 4 3 2 1 0  ||  B OP
    ------+--------------++------------
    0 0   | x x x x x x  ||  0 10
    x 1   | x x x x x x  ||  1 10
    1 x   | x x 0 0 0 0  ||  0 10
    1 x   | x x 0 0 1 0  ||  1 10
    1 x   | x x 0 1 0 0  ||  0 00
    1 x   | x x 0 1 0 1  ||  0 01
    1 x   | x x 1 0 1 0  ||  1 11
    

• How would we implement this?
• A circuit for each of the three output bits.
• Must decide when each output bit is 1.
• We do this one output bit at a time.
  
  

1. When is Bnegate (called Op2 in book) asserted?
   
   • Those rows where its bit is 1, rows 2, 4, and 7.

         ALUOp | Funct      
         1 0   | 5 4 3 2 1 0
         ------+------------
         x 1   | x x x x x x
         1 x   | x x 0 0 1 0
         1 x   | x x 1 0 1 0
         

   • Notice that, in the 5 rows with ALUOp=1x, F1=1 is enough to distinugish the two rows where Bnegate is asserted.
   • This gives

         ALUOp | Funct       
         1 0   | 5 4 3 2 1 0 
         ------+-------------
         x 1   | x x x x x x 
         1 x   | x x x x 1 x 
         

   • Hence Bnegate is ALUOp0 + (ALUOp1 F1)
   
   
2. When is OP1 asserted?
   • Again we begin with the rows where its bit is one

         ALUOp | Funct      
         1 0   | 5 4 3 2 1 0
         ------+------------
         0 0   | x x x x x x
         x 1   | x x x x x x
         1 x   | x x 0 0 0 0
         1 x   | x x 0 0 1 0
         1 x   | x x 1 0 1 0
         

   • Again inspection of the 5 rows with ALUOp=1x yields one F bit that distinguishes when OP1 is asserted, namely F2=0

         ALUOp | Funct      
         1 0   | 5 4 3 2 1 0
         ------+------------
         0 0   | x x x x x x
         x 1   | x x x x x x
         1 x   | x x x 0 x x
         

   • Since x 1 in the second row is really 0 1, rows 1 and 2 can be combined to give

         ALUOp | Funct      
         1 0   | 5 4 3 2 1 0
         ------+------------
         0 x   | x x x x x x
         1 x   | x x x 0 x x
         

   • Now we can use the first row to enlarge the scope of the last row

         ALUOp | Funct      
         1 0   | 5 4 3 2 1 0
         ------+------------
         0 x   | x x x x x x
         x x   | x x x 0 x x
         

   • So OP1 = NOT ALUOp1 + NOT F2
   
   
3. When is OP0 asserted?
   • Start with the rows where its bit is set.

         ALUOp | Funct      
         1 0   | 5 4 3 2 1 0
         ------+------------
         1 x   | x x 0 1 0 1
         1 x   | x x 1 0 1 0
         

   • But again looking at all the rows where ALUOp=1x we see that the two rows where OP0 is asserted are characterized by just two Function bits

         ALUOp | Funct      
         1 0   | 5 4 3 2 1 0
         ------+------------
         1 x   | x x x x x 1
         1 x   | x x 1 x x x
         

   • So OP0 is ALUOp1 F0 + ALUOp1 F3

The circuit is then easy.