Computer Architecture
1999-2000 Fall
MW 3:30-4:45
Ciww 109

Allan Gottlieb
gottlieb@nyu.edu
http://allan.ultra.nyu.edu/~gottlieb
715 Broadway, Room 1001
212-998-3344
609-951-2707
email is best


======== START LECTURE #9 ========

Now we augment the ALU so that we can perform subtraction (as well as addition, AND, and OR).

1-bit ALU with ADD, SUB, AND, OR is

Implementing addition and subtraction

  1. To implement addition we use opcode 10 as before and de-assert both b-invert and Cin.
  2. To implement subtraction we still use opcode 10 but we assert both b-invert and Cin.










32-bit version is simply a bunch of these.



(More or less) all ALUs do AND, OR, ADD, SUB. Now we want to customize our ALU for the MIPS architecture. Extra requirements for MIPS ALU:

  1. slt set-less-than








    Homework: figure out correct rule, i.e. prob 4.23. Hint: when an overflow occurs the sign bit is definitely wrong (so the complement of the sign bit is right).
    1. Overflows
      • The HOB ALU is already unique (outputs SET).
      • Need to enhance it some more to produce the overflow output.
      • Recall that we gave the rule for overflow. You need to examine:
        • Whether the operation is add or sub (binvert).
        • The sign of A.
        • The sign of B.
        • The sign of the result.
        • Since this is the HOB we have all the sign bits.
        • The book also uses Cout, but this appears to be an error.





    1. Zero Detect
      • To see if all bits are zero just need NOR of all the bits
      • Conceptually trivially but does require some wiring

    2. Observation: The initial Cin and Binvert are always the same. So just use one input called Bnegate.

    The Final Result is

    The symbol used for an ALU is on the right

    What are the control lines?

    What functions can we perform?

    What (3-bit) values for the control lines do we need for each function? The control lines are Bnegate (1-bit) and Operation (2-bits)
    and 0 00
    or 0 01
    add 0 10
    sub 1 10
    slt 1 11