======== START LECTURE #26 ========

Improving Bus Performance

These improvements mostly come at the cost of increased expense and/or complexity.

  1. Hierarchy of buses.

  2. Synchronous instead of asynchronous protocols.
  3. Wider data path: Use more wires, send more at once.

  4. Separate address and data lines: Same as above.

  5. Block transfers: Permit a single transaction to transfer more than one busload of data. Saves the time to release and acquire the bus, but the protocol is more complex.

  6. Obtaining bus access:
OptionHigh performanceLow cost
bus widthseparate address and data lines multiplex address and data lines
data widthwidenarrow
transfer sizemultiple bus loadssingle bus loads
bus mastersmultiplesingle
clockingsynchronousasynchronous

Do on the board the example on pages 665-666