Adders

1. We have done what is called a ripple carry adder.
   The carry "ripples" from one bit to the next (LOB to HOB).
   So the time required is proportional to the wordlength.
   Each carry can be computed with two levels of logic (any function can be so computed) hence the number of gate delays is 2*wordsize.
2. What about doing the entire 32 (or 64) bit adder with 2 levels of logic?
   • Such a circuit clearly exists. Why?
   • Ans: A two levels of logic circuit exists for any function.
   • But it would be very expensive: many gates and wires.
   • The big problem: The AND and OR gates have high fan-in, i.e., they have a large number of inputs. It is not true that a 64-input AND takes the same time as a 2-input AND.
   • Unless you are doing full custom VLSI, you get a toolbox of primative functions (say 4 input NAND) and must build from that
3. There are faster adders, e.g. carry lookahead and carry save. We will study the carry lookahead.

Carry Lookahead adders

We did a ripple adder

• The delay proportional to # bits.
• In detail, each bit the CarryOut uses two levels of logic after the CarryIn is stable.
• So the delay for calculating an n-bit sum is 2n gate delays.
• For 4 bits the delay is 8
• For 16, delay is 32
• For 32, delay is 64
• For 64, delay is 128

We will now do the carry lookahead adder, which is much faster, especially for many bit (e.g. 64 bit) addition.

For each bit we can in one gate delay calculate

    generate a carry    gi = ai bi

    propogate a carry   pi = ai+bi

H&P give a plumbing analogue for generate and propogate.

Given the generates and propogates, we can calculate all the carries for a 4-bit addition (recall that c0=Cin is an input) as follows

c1 = g0 + p0 c0

c2 = g1 + p1 c1 = g1 + p1 g0 + p1 p0 c0

c3 = g2 + p2 c2 = g2 + p2 g1 + p2 p1 g0 + p2 p1 p0 c0

c4 = g3 + p3 c3 = g3 + p3 g2 + p3 p2 g1 + p3 p2 p1 g0 + p3 p2 p1 p0 c0

Thus we can calculate c1 ... c4 in just two additional gate delays (where we assume one gate can accept upto 5 inputs). Since we get gi and pi after one gate delay, the total delay for calculating all the carries is 3 (this includes c4=CarryOut)

Each bit of the sum si can be calculated in 2 gate delays given ai, bi, and ci. Thus 5 gate delays after we are given a, b and CarryIn, we have calculated s and CarryOut

So for 4-bit addition the faster adder takes time 5 and the slower adder time 8.

Now we want to put four of these together to get a fast 16-bit adder. Again we are assuming a gate can accept upto 5 inputs. It is important that the number of inputs per gate does not grow with the size of the numbers to add. If the technology available supplies only 4-input gates, we would use groups of 3 bits rather than four.

We start by determining ``supergenerate'' and ``superpropogate'' bits. The super propogate indicates whether the 4-bit adder constructed above generates a CarryOut or propogates a CarryIn to a CarryOut

P0 = p3 p2 p1 p0          Does the low order 4-bit adder
                          propogate a carry?
P1 = p7 p6 p5 p4

P2 = p11 p10 p9 p8

P3 = p15 p14 p13 p12      Does the high order 4-bit adder
                          propogate a carry?


G0 = g3 + p3 g2 + p3 p2 g1 + p3 p2 p1 g0        Does low order 4-bit
                                                adder generate a carry
G1 = g7 + p7 g6 + p7 p6 g5 + p7 p6 p5 g4

G2 = g11 + p11 g10 + p11 p10 g9 + p11 p10 p9 g8

G3 = g15 + p15 g14 + p15 p14 g13 + p15 p14 p13 g12


C1 = G0 + P0 c0

C2 = G1 + P1 C1 = G1 + P1 G0 + P1 P0 c0

C3 = G2 + P2 C2 = G2 + P2 G1 + P2 P1 G0 + P2 P1 P0 c0

C4 = G3 + P3 C3 = G3 + P3 G2 + P3 P2 G1 + P3 P2 P1 G0 + P3 P2 P1 P0 c0

From these C's you just need to do a 4-bit CLA since the C's are the CarryIns for each group of 4-bits out of the 16-bits.

How long does this take, again assuming 5 input gates?

• We calculate the P's one gate delay after we have the p's. Since the pj's are determined 1 gate delay after we are given the a's and b's. So we have all Pi 2 gate delays after we start.
• The G's are determined 2 gate delays after we have the g's and p's. So the G's are done 3 gate delays after we start.
• The C's are determined 2 gate delays after the P's and G's. So the C's are done 5 gate delays after we start.
• Now the C's are sent back to the 4-bit adders, which have already calculated the p's and g's. Hence the c's are calculated in 2 more gate delays (7 total) and the s's 2 more after that (9 total).
• So a 16-bit CLA takes 9 cycles instead of 32 for a ripple carry adder.

Some pictures follow.

Take our original picture of the 4-bit CLA and collapse the details so it looks like.

Next include the logic to calculate P and G

Now put four of these with a CLA block (to calculate C's from P's, G's and Cin) and we get a 16-bit CLA. Note that we do not use the Cout from the 4-bit CLAs.

Note that the tall skinny box is general. It takes 4 Ps 4Gs and Cin and calculates 4Cs. The Ps can be propogates, superpropogates, superduperpropogates, etc. That is, you take 4 of these 16-bit CLAs and the same tall skinny box and you get a 64-bit CLA.

Homework: 4.44, 4.45