======== START LECTURE #4 ========

PLAs--Programmable Logic Arrays

Idea is to make use of the algorithmic way you can look at a TT and produce a circuit diagram in the sums of product form.

Consider the following TT from the book (page B-13)

     A | B | C || D | E | F
     --+---+---++---+---+--
     O | 0 | 0 || 0 | 0 | 0
     0 | 0 | 1 || 1 | 0 | 0
     0 | 1 | 0 || 1 | 0 | 0
     0 | 1 | 1 || 1 | 1 | 0
     1 | 0 | 0 || 1 | 0 | 0
     1 | 0 | 1 || 1 | 1 | 0
     1 | 1 | 0 || 1 | 1 | 0
     1 | 1 | 1 || 1 | 0 | 1

Recall that there is a big OR for each output
We can see that there are 7 product terms that will be used in one or more of the ORs (in fact all seven will be used in D, but that is special to this example)
Each of these product terms is called a Minterm
So we need a bunch of ANDs taking A, B, C as inputs (and their complements A', B', and C')
This is called an AND plane and the collection of ORs mentioned above is called a OR plane.
Convert to sum of product forms (only NOTs on vbles)

Here is the circuit diagram for this truth table.

Here it is redrawn

This figure shows more clearly the AND plane, the OR plane, and the minterms.
Rather than having bubbles (i.e., custom and gates that invert), we simply invert each input once and send the inverted signal all the way accross.
AND gates are shown as vertical lines; ORs as horizontal.
Note the dots to represent connections

Finally, it can be redrawn in a more abstract form.

When a PLA is manufactured all the connections have been specified. That is, a PLA is specific for a given circuit. It is somewhat of a misnomer since it is notprogrammable by the user

Homework: B.10 and B.11

Can also have a PAL or Programmable array logic in which the final dots are specified by the user. The manufacturer produces a ``sea of gates''; the user programs it to the desired logic function.

Homework: Read B-5

ROMs

One way to implement a mathematical (or C) function (without side effects) is to perform a table lookup.

A ROM (Read Only Memory) is the analogous way to implement a logic function.

For a math function f we start with x and get f(x).
For a ROM with start with the address and get the value stored at that address.
Normally math functions are defined for an infinite number of values, for example f(x) = 3x for all real numbers x
We can't build an infinite ROM (sorry), so we are only interested in functions defined for a finite number of values. Today a million is OK a billion is too big.
To create the ROM for the function f(3)=4, f(6)=20 all other values undefined just have the ROM store 4 in address 3 and 20 in address 6
Consider a function defined for all n-bit numbers (say n=20) and having a k-bit output for each input.
- View each n-bit input as n 1-bit inputs.
- View each k-bit output as k 1-bit outputs.
- Since there are 2^n inputs and each requires a k 1-bit output, there are a total of (2^n)k bits of output, i.e. the ROM must hold (2^n)k bits.
- Imagine a truth table with n inputs and k outputs. The total number of output bits is again (2^n)k (2^n rows and k output columns).
Thus the ROM implements a truth table, i.e. is a logic function.

Important: The ROM is does not have state. It is still a combinational circuit. That is, it does not represent ``memory''. The reason is that once a ROM is manufactured, the output depends only on the input.

A PROM is a programmable ROM. That is you buy the ROM with ``nothing'' in its memory and then before it is placed in the circuit you load the memory, and never change it.

An EPROM is an erasable PROM. It costs more but if you decide to change its memory this is possible (but is slow).

``Normal'' EPROMs are erased by some ultraviolet light process. But EEPROMs (electrically erasable PROMS) are faster and are done electronically.

All these EPROMS are erasable not writable, i.e. you can't just change one bit.

A ROM is similar to PLA

Both can implement any truth table, in principle.
A 2Mx8 ROM can really implment any truth table with 21 inputs (2^21=2M) and 8 outputs.
- It stores 2M bytes
- In ROM-speak, it has 21 address pins and 8 data pins
A PLA with 21 inputs and 8 outputs might need to have 2M minterms (AND gates).
- The number of minterms depends on the truth table itself.
- For normal TTs with 21 inputs the number of minterms is MUCH less than 2^21.
- The PLA is manufactured with the number of minterms needed
Compare a PAL with a PROM
- Both can in principle implement any TT
- Both are user programmable
- A PROM with n inputs and k outputs can implement any TT with n inputs and k outputs.
- A PAL does not have enough gates for all possibilities since most TTs with n inputs and k outputs don't require nearly (2^n)k gates.

Don't Cares

Sometimes not all the input and output entries in a TT are needed. We indicate this with an X and it can result in a smaller truth table.
Input don't cares.
- The output doesn't depend on all inputs, i.e. the output has the same value no matter what value this input has.
- We saw this when we did muxes
Output don't cares
- For some input values, either output is OK.
  - This input combination is impossible.
  - For this input combination, the given output is not used (perhaps it is ``muxed out'' downstream)

Example

If A or C is true, then D is true (independent of B).
If A or B is true, the output E is true.
F is true if exactly one of the inputs is true, but we don't care about the value of F if both D and E are true

Full truth table

     A   B   C || D   E   F
     ----------++----------
     0   0   0 || 0   0   0
     0   0   1 || 1   0   1
     0   1   0 || 0   1   1
     0   1   1 || 1   1   0
     1   0   0 || 1   1   1
     1   0   1 || 1   1   0
     1   1   0 || 1   1   0
     1   1   1 || 1   1   1

Put in the output don't cares

     A   B   C || D   E   F
     ----------++----------
     0   0   0 || 0   0   0
     0   0   1 || 1   0   1
     0   1   0 || 0   1   1
     0   1   1 || 1   1   X
     1   0   0 || 1   1   X
     1   0   1 || 1   1   X
     1   1   0 || 1   1   X
     1   1   1 || 1   1   X

Now do the input don't cares

B=C=1 ==> D=E=11 ==> F=X ==> A=X
A=1 ==> D=E=11 ==> F=X ==> B=C=X

     A   B   C || D   E   F
     ----------++----------
     0   0   0 || 0   0   0
     0   0   1 || 1   0   1
     0   1   0 || 0   1   1
     X   1   1 || 1   1   X
     1   X   X || 1   1   X

These don't cares are important for logic minimization. Compare the number of gates needed for the full TT and the reduced TT. There are techniques for minimizing logic, but we will not cover them.

Arrays of Logic Elements

Do the same thing to many signals
Draw thicker lines and use the "by n" notation.
Diagram below shows 32- bit 2-way mux and implementation with 32 muxes
A Bus is a collection of data lines treated as a single logical (n-bit) value.
Use an array of logic elements to process a bus. For example, the above mux switches between 2 32-bit buses.

32-bit mux

*********** Big Change Coming ***********

Sequential Circuits, Memory, and State

Why do we want to have state?

Memory (i.e. ram not just rom or prom)
Counters
Reducing gate count
- Multiplier would be quadradic in comb logic.
- With sequential logic (state) can do in linear.
  - What follows is unofficial (i.e. too fast to understand)
  - Shift register holds partial sum
  - Real slick is to share this shift reg with multiplier
  - We will do this circuit later in the course

Assume you have a real OR gate. Assume the two inputs are both zero for an hour. At time t one input becomes 1. The output will OSCILLATE for a while before settling on exactly 1. We want to be sure we don't look at the answer before its ready.