==================== Start of Lecture 2 ===========================

Homework 2.1
             Eine Kleine Hardware
             (with appologies to Mozart)
          (assumes "hardware" is femine ...
         otherwise Ein Kleiner or Ein Keines)


Figure 1 from book

       Correction
       Expansion

Hardware reset

    Get part of system in a known state and trans cntl to known addr

Bootstrap program/loader
      
    Get OS into system

Interrupts

    Hardware (from controllers)

    Software (system calls; become traps)

    On interrupt, control is transferred to known location.
    There can be many different kinds of interrupts distinguished by

        Transferred addr (interrupt vector contains addrs)
        Some state (e.g. specific register in the case trap)
        Polling devices and asking

    Show asychrony with interrupts.

    Unsolicited subroutine call (especially hw interrupts).

    Disabling interrupts (solution to first homework problem)

    Interrupt driven

        OS sits in idle loop waiting for interrupt.

I/O

    Synchronous gives favorable semantics but bad perf
    Async the reverse.
    Normal is for OS to use async and give user sync

Implementing OS I/O (i.e. real I/0)

    Want to be async, i.e. many I/Os + computation active
    Can poll device
    Can use interrupts
        CPU gets data from controler one interrupt per buffer load
        Can use DMA to avoid many interrupts and lighten bus load

Implementing user I/O (sync)

    Block user process
    Record status in device status table
    Field interrupt from device
    Make user process ready

Storage

    Model is program + data in "main memory"
    Data accessed by loads and stores (and memory operands)
    Instructions fetched implicitly

    Doesn't all fit
    Volatile

    Secondary storage
    on-demand fetching

Main memory

    Roughly 10MB-1GB

    Program and data resides here when accessed
        (at least is addressed here)

    I/O controllers have memory
        special instructions
        memory mapped I/O

Disks

    sector
    track
    cylinder
    platter
    head
    arm
    arm assembly

    fixed head disk

    transfer rate 10-40 MB/S from cache; less from platter

    100MB-10GB

    heads fly except on floppys

    amazing mechanical devices (1000 cylinders)

    disk has electronics to raise level of abstraction and caches

    disk controller (raise level of abstraction) and caches

    drum (good old days)

    optical (CDROM; DVD; writable; write once)

Tapes

Hierarchy

    Fast, Large, Cheap -- Pick 2 (maybe 1)

    Migration
    Caching
        Consistency
        Especially for MP systems
        DMA I/O conroller like another processor

Homework 2.10

Hardware Protection

    Users from each other

    Users from themselves

    User/supervisor mode

        I/O is supervisor
        user traps to supervisor mode but not to user's code

Homework 2.3, 2.4, 2.6 2.8 (just one difficulty), 2.9

====================  End lecture 2 =============================