HOMEWORK 5.1, 5.11 (just datapaths not control).

Lab 2.  Due in ONE week.  Modify lab1 to deal with slt, zero detect,
overflow.  That is, Figure 4.17

Overflow

    Will EXPLAIN for addition of nonnegatives and give rule for all.

    Assume 32 bit addition of nonnegs.  So numbers are 31 bits with
    sign 0.

    How can you get an overflow?

    The 31 bit addition gives a 32-bit sum.

    This looks like a negative number!  That is the sign is 1.

    Rule:  When adding nonnegs, overflow iff result sign is 1.

    Remaining rules all say get an overflow if sign bit "wrong"

        Rule: When add negatives, overflow iff result sign is 0.

        Rule: When adding neg and nonneg, never overflows

        Rule: When subtracting two negs or two nonnegs, never overflow

        Rule: When subtracting neg from nonneg, overflow if result
        sign is 1

        Rule: When subtracting nonneg from net, overflow if result
        sign is 0

    All this can be summarized as

    GRAND RULE overflow iff carry into sign bit != carry out of sign
    bit

        OVERFLOW = CARRY-IN XOR CARRY-OUT

        For adding nonnegs the carry out is surely 0
        and you need a 0 carry in to get a result with positive sign

        For adding negs the carry out is surely 1
        and you need a 1 carry in to get result with negative sign

Modification to slt

    Recall that for slt we want to know if x-y is negative.

    Sounds like subtraction

    But we want the correct sign even if overflow

    If overflow the sign is wrong so the correct sign is
    SUM[0] XOR OVERFLOW

---------------- The control for the datapath ----------------

We start with figure 5.14, which shows the data path.

We need to set the muxes.

We need to give the three ALU cntl lines: 1-bit Bnegate and 2-bit OP

    And     0 00
    Or      0 01
    Add     0 10
    Sub     1 10
    Set-LT  1 11

HOMEWORK what happens if we use 1 00?  if we use 1 01?
Ignore the funny business in the HOB.
The funny business "ruins" these ops

What information do we have to decide on the muxes and alu cntl lines?

The instruction!

    Opcode field (6 bits)

    For R-type the funct field (6 bits)

So no problem, just do a truth table.

    12 inputs, 3 outputs

    4096 rows, 15 columns, > 60K entries

    HELP!

We will let the main control (to be done later) "summarize"
the opcode for us.  It will generate a 2-bit field ALUop

    ALUop   Action needed by ALU

    00      Addition (for load and store)
    01      Subtraction (for beq)
    10      Determined by funct field (R-type instruction)
    11      Not used

So now we have 8 inputs (2+6) and 3 outputs

    256 rows, 11 columns; ~2800 entries

Certainly easy for automation ... but we will be clever

    We only have 8 MIPS instructions that use the ALU (fig 5.15).               

    Funct only used for 10

    11 impossible ==> 01 = X1   and    10 = 1X

So we get

ALUop | Funct        ||  Bnegate:OP
0 1   | 5 4 3 2 1 0  ||  B OP
------+--------------++------------
      |              ||
0 0   | x x x x x x  ||  0 10
x 1   | x x x x x x  ||  1 10
1 x   | x x 0 0 0 0  ||  0 10
1 x   | x x 0 0 1 0  ||  1 10
1 x   | x x 0 1 0 0  ||  0 00
1 x   | x x 0 1 0 1  ||  1 11

How would we implement this?

A circuit for each of the three output bits.

Just decide when the individual output bit is 1 (figure 5.17)

The circuit is then easy (5.18)

Now we need the main control

    setting the four muxes

    Writing the registers

    Writing the memory

    Reading the memory ??? not really (well maybe ... for dram)

    Calculating ALUop

So 9 (really 8 bits)

Fig 5.20 shows were these occur.

They all are determined by the opcode

The MIPS instruction set is fairly regular.  Most fields we need
are always in the same place in the instruction.

    Opcode (called Op[5-0]) always in 31-26

    Regs to be read always 25-21 and 20-16 (R-type, beq, store)

    Base reg always 25-21 (load store)

    Offset always 15-0

    Oops: Reg to be written EITHER 20-16 (load) OR 15-11 (R-type) MUX!!



Fig 5.21 describes each signal

    MemRead:  Memory delivers the value stored at the specified addr

    MemWrite: Memory stores the specified value at the specified addr

    ALUSrc:   Second ALU operand comes from (reg-file / sign-ext-immediate)

    RegDst:   Number of reg to write comes from the (rt / rd) field

    RegWrite: Reg-file stores the specified value in the specified register

    PCSrc:    New PC is Old PC + (4 / shifted-branch-target-disp)

    MemtoReg: Value written in reg-file comes from (alu / mem)    

Fig 5.22 shows the wires for control

We are interested in four opcodes

    R-type
    load
    store
    BEQ

Do a stage play

Fig 5.23 summarizes the play (i.e. the control lines).

Fig 5.27 (from FIFTH edition, an improvement to 5.30 in fourth
edition) shows the control signal settings for each opcode.

Now it is straightforward but tedious to get the logic equations

Result is figure 5.31

HOMEWORK 5.1 5.11 control, 5.2, 5.12 

New instruction format, unconditional jump

    opcode  addr
    31-26   25-0

    Addr is word addr; bot 2 bits of PC always 0

    Top 4 bits of PC stay as they were (AFTER incr by 4)

    Easy to add.  My overlay to fig 5.22.