Simulating Combinatorial Circuits at the Gate Level

    Write a procedure for each logic box

        Parameters for each input and output

        (Local) variable for each (internal) wire

        Can only do AND OR XOR NOT

            In the C language & | ^ ~

            Other languages similar

        No conditional assignment; the output is a FUNCTION of the
        input

        Single assignment to each variable.
        Multiple assignments would correspond to a cycle

        Bus (set of signals) represented by array

        Testing

            Exhaustive possible for 1-bit cases

            Cleverness for n-bit cases (n=32, say)

HANDOUT full-adder.c  4add.c.  These are on the web

Lab 1 Do the equivalent for 32-bit-alu

Extra requirement for MIPS alu: slt  set-if-less-than

    Result reg is 1 if a < b
    Result reg is 0 if a >= b

    So need to make the LOB of result = sign bit of a subtraction and
    the rest of the result bits are always zero.

    Idea #1.  Give the mux another input.
    This input is brought in from outside the bit cell.
    That is for this setting of the mux, cell copies an input to its output.
    Set the mux to deliver this output when an slt is requested. Fig V

    Idea #2.  Bring out the result of the adder (BEFORE the mux) Fig W.
    Only needed for the HOB (i.e. sign)
    Take this new output from the HOB and connect it to
    the new input in idea #1 for the LOB.
    The new input for other bits are set to zero.

    Problem:  This is wrong!
    Take example using 3 bits (i.e. -4 .. 3).
    Try slt on -3 and 2.
    Subtraction (-3 - 2) should give -5 saying that -3 < 2.
    But -3 - 2 gives +3 !!
    Really it give OVERFLOW.
    But slt -3 -2 should not overflow.

    Solution: Need the correct rule for less than (not just sign of
    subtraction)

HOMEWORK: figure out correct rule, i.e. prob 4.25

Extra requirement.  Deal with overflows

    The 1 bit alu for hob really is different from the others Fig X (4.15).

Extra requirement.  Zero detect

    Large NOR

Observation:  The initial Cin and Binvert are always the same.
So just use one input called Bnegate

Final Result is Figure Y (4.17)

Symbol for the alu is fig Z (4.18)

What are the control lines?

    Bnegate
    OP
    
What functions can we perform

    and
    or
    add
    sub
    set on less than


What (3-bit) control lines do we need for each?

    and 0 00
    or  0 01
    add 0 01
    sub 0 01
    slt 1 11

Adder with just 2 levels of logic

    Clearly exists

    Expensive

    Large fan-in means not as fast as 2 simple levels of logic

Carry Lookahead adders

    We did ripple adder, delay proportional to # bits

    For each bit we can immediately (one gate delay) calculate

        generate a carry    gi = ai bi

        propogate a carry   pi = ai+bi

    Now we can calculate all the carries (4 bit) just given c0=Cin

        c1 = g0 + p0 c0

        c2 = g1 + p1 c1 = g1 + p1 g0 + p1 p0 c0

        c3 =

        c4 = g3 + p3 g2 + ... + p3 p2 p1 p0 c0

    Thus can calculate c1 ... c4 in just two (5-input) gate delays

    Now put 4 of these together to get all the 16-bit carries

        P0 = p3 p2 p1 p0

        P1 = p7 p6 p5 p4

        P2 = 

        P3 = p15 p14 p13 p12


        G0 = g3 + p3 g2 + ... + p3 p2 p1 g0

        G1 = g7 + p7 g6 + ... + p7 p6 p5 g4

        G2 =

        G3 = g15 + p15 g14 + ... p15 p14 p13 g12


        C1 = G0 + P0 c0

        C2 = G1 + P1 C1 = G1 + P1 G0 + P1 P0 c0

        C3 =

        C4 = G3 + P3 G2 + ... + P3 P2 P1 P0 c0