NOTE: The real story on counters is told in Figure P. HOMEWORK B.13 Now you can really do it. Register File Set of registers each numbered Supply reg#, write line, and data (if a write) Often have several read and write ports so that several registers can be read and written during one cycle. Can read and write same reg same cycle (read old value) We will do 2 read ports and one write port since that is needed for ALU ops. NOT adequate for superscalar To read just need mux from register file to select correct register. Have one of these for each read port For writes use a decoder on register number to determine which register to write Figure N (B.20 from book). Note that 2 errors were fixed. SRAMS and DRAMS External interface is Figure O (B.21 from book) (Sadly) we will not look inside. Following is unofficial Different from above because too many wires and muxes too big Two stage decode Tri-state buffers instead of mux for SRAM DRAM latches whole row but outputs only one (or a few) column(s) So can speed up access to elts in same Row Merged DRAM + CPU a new hot topic Error Correction Skipped There are other kinds of flip-flops T, J-K. Also one could learn about excitation tables for each. We will NOT (H&P doesn't either). If interested, see Mano Finite State Machines Skipped Timing Methodologies Skipped ------------------ End Appendix B ------------ ================ End Lecture 5 ================ ================ Start Lecture 6 ================ ---------------- Start Chapter 1---------------- HOMEWORK READ chapter 1. Do 1.1 -- 1.26 (really one matching question) Do 1.27 to 1.44 (another matching question) 1.45 (and do 7200 RPM and 10,000 RPM) 1.46, 1.50 ---------------- End Chapter 1 ---------------- ---------------- Start Chapter 3 ---------------- HOMEWORK Read sections 3.1 3.2 3.3 3.4 Representing instructions in the Computer (MIPS) 32 32-bit registers Register 0 is always 0 HOMEWORK 3.2 R-type instruction (R for register) op rs rt rd shamt funct 6 5 5 5 5 6 rs,rt are source operands rd is destination shift amount funct used for op=0 to distinguish alu ops add/sub $1,$2,$3 op=0, funct tells add/sub reg1 <-- reg2 + reg3 the regs can be the same (doubles the value in the reg) I-type (why I?) op rs rt address 6 5 5 16 rs is a source reg rt is a destination reg Transfers to/from memory often in words (32-bits) But the machine is byte addressible So shift the address left two bits lw/sw $1,addr($2) machine format is op 2 1 addr $1 <-- Mem[$2+addr] $1 --> Mem[$2+addr] Note how field sizes of R-type and I-type correspond. Will be important later The type is determined by the op. Branching instruction slt (set less-then) R-type Slt $3,$8,$2 reg3 <-- (1 if reg8