NOTE:  The real story on counters is told in Figure P.

HOMEWORK B.13  Now you can really do it.

    Register File

        Set of registers each numbered
        Supply reg#, write line, and data (if a write)

        Often have several read and write ports so that several
        registers can be read and written during one cycle.

        Can read and write same reg same cycle (read old value)

        We will do 2 read ports and one write port since that is
        needed for ALU ops.

            NOT adequate for superscalar

        To read just need mux from register file to select correct
        register.

            Have one of these for each read port

        For writes use a decoder on register number to determine which
        register to write

        Figure N (B.20 from book).
            Note that 2 errors were fixed.

    SRAMS and DRAMS

        External interface is Figure O (B.21 from book)

        (Sadly) we will not look inside.  Following is unofficial

        Different from above because too many wires and muxes too big

        Two stage decode

        Tri-state buffers instead of mux for SRAM

        DRAM latches whole row but outputs only one (or a few) column(s)

            So can speed up access to elts in same Row

            Merged DRAM + CPU a new hot topic

    Error Correction

        Skipped

    There are other kinds of flip-flops T, J-K.  Also one could learn
    about excitation tables for each.  We will NOT (H&P doesn't either).
    If interested, see Mano

Finite State Machines

    Skipped

Timing Methodologies

    Skipped

------------------ End Appendix B ------------