IMPORTANT NOTE:  Class will be held each thursday BUT
No assignments will be due 2nd, 16th, or 23.
Any homework ASSIGNED on those days will be available on the
web.  These notes are now web available as
http://allan.ultra.nyu.edu/arch/class-notes
So homework assigned this week (please number it HW#4) will
be due on the 9th (14 days from today).
HW#5 (assigned on the 9th), HW#6 (16th), and HW#7 (23)
will all be due on the 30th.  Please have each HW on separate pages.
On 30th we will schedule the midterm, the midterm will NOT be on
the 30th.  That is the day we will decide on the midterm date and on
how much will be covered.

    CLOCKED memory

        what we are really interested in.

        clocked latch

            output changes when input changes and the clock is asserted

            "level sensitive" rather than "edge triggered"
            sometimes called "transparent"

            we won't use these in designs but will show how to build one

            fig J is a D (clocked) latch.  D for "data"

        flip-flop changes on active edge

            NOT transparent

            Fig K is D flip flop built from D latches

                This one has the falling edge as active edge

                Sometimes called a master-slave flip-flop

                Note box around main structure and letters reused
                with different meaning (block structure a la algol)

                Master latch is set during the time clock is asserted.
                Remember that the latch is transparent, i.e. follows
                its input when its clock is asserted.  But the second
                latch is ignoring its input at this time.  When the
                clock falls, the 2nd latch pays attention and the
                first latch keeps producing whatever D was at
                fall-time.

                Actually D must remain constant for some time around
                the active edge.

                    Must be valid for set-up time before and hold time
                    after

HOMEWORK Try moving the inverter to the other latch (see fig K).
This should give rising edge as active edge.

                Flip flops give counters.

                    Explained next lecture

Homework B.13  Don't worry if it seems hard

    Register

        Just an array of D flip-flops with a write line, fig M.

        Must have write line and data valid during setup and hold
        times