Sneaky way to see that NAND is universal
(Fig sneaky)  Do this lecture 3 after hw for lect 2.

Half Adder

    Inputs X and Y

    Outputs S and Co (carry out)

    No Carry-in

    Draw TT

HOMEWORK Draw logic diagram

Full Adder

    Inputs X, Y and Ci

    Output S and Co

    S = # 1s in X, Y, Ci is odd

    Co = #1s is at least 2

HOMEWORK Draw TT (8 rows), show S = X XOR Y XOR Ci,
show Co = XY + (X XOR Y)Z

    Draw circuit using formulas for S and Co from homework

    How about 4 bit adder ?
        Do it.

    How about n bit adder ?

        Linear complexity

        Called ripple carry

        Faster methods exist



PLAs

    Programmable Logic Array

    Fig G (from book)
    Minterms
    Start with a logical formula
    Convert to sum of product forms (only NOTs on vbles)

    Can also have a PAL in which the final dots are specified
    later.  Mass produce the sea of gates first.

HOMEWORK B-5

ROM

    Another way to implement a logic function.

    For n inputs and k outputs need (2^n)k bits stored,
    namely the columns for the output vbles in the TT

    NOT considered state.
        Once the ROM is made, the output depends only on the input.

    Similar to PLA
        Fully decoded

    PROMs, EPROMS, EEPROMs

Don't Cares

    Input don't cares
    Output don't cares
    Input DC example was mux
    Do output DC from book (Fig H)


Arrays of Logic Elements

    Do the same thing to many signals

    Draw thicker lines and use the "by n" notation.

    Show dia for 8 bit 2-way mux and implementation with 8 muxes

    Bus is a collection of data lines treated as a single logical
    (n-bit) value.

    Use arrays of logic elements to process buses
        The above mux switches between 2 8-bit buses.

-------------  Big Change Coming --------

Why do we want to have state?

    Memory (i.e. ram not just rom or prom)

    Counters

    Reducing gate count

        Multiplier would be quadradic in comb logic.

        With sequential logic (state) can do in linear.

            What follows is unofficial (i.e. too fast to understand)

            Shift register holds partial sum

            Real slick is to share this shift reg with mulitplier

Assume you have a real OR gate.  Assume the two inputs are both
zero for an hour.  At time t one input becomes 1.  The output will
OSCILLATE for a while before settling on exactly 1.  We want to be
sure we don't look at the answer before its ready.

Clocks

    Frequency
    Period
    Rising Edge; falling edge

    We use edge-trigger logic
        State changes occur only on a clock edge
        Will explain later what this really means

    Active edge
        The edge on which changes occur
        Choice is technology dependent

    Synchronous system

        state-element ----> comb circuit  -----> state-element

        state-elements have clock as an input

            can change state only at active edge

            produces output ALWAYS; based on current state

        all signals written to state elements must be valid at active edge

        Eg.  If cycle time is 10ns make sure combinational circuit
        used to compute new state values completes in 10ns

        So state elements change on active edge, comb circuit
        stablizes between active edges

        Can have

            +---> state-element -----> comb circuit ---+
            |                                          |
            |                                          |
            +------------------------------------------+

Memory

    We want CLOCKED memory and will only use CLOCKED memory in our
    designs.  However for simplicity we first describe how to make

    UNCLOCKED memory

        S-R latch (set-reset)

        Fig I

        DONT assert both S and R at once

        S asserted sets the latch Q is true Q_ false
        R asserted resets the latch Q flase Q_ true

        Neither asserted Q and Q_ remain as they were
            This is the MEMORY