[SMT-LIB] Research position in formal verification in the advanced research center of Atrenta EU

[Fahim Rahim]

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Job Description:
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The research activity will aim at investigating and developing novel

techniques, methodologies and support tools for the verification of circuit designs in particular the use

of Satisfiability Modulo Theories (SMT), however researcher with background on other verification techniques are also

encouraged to apply.




Candidate Profile:

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World class researcher in EE/CS/Math (particularly formal theory), familiar with predicate logic,
temporal logic (e.g., CTL, LTL), model checking, familiar with complexity of algorithms,
very strong in algorithm development -- including design and implementation of large programs,
very  strong in mathematical considerations in the development of CAD tools/EDA and familiarity with design practice.
Intimate knowledge of solvers such as  BDD, SAT, ATPG, SMT and symbolic simulation algorithms.
Capability of working with prospective customers. Experience in a Semiconductor company is helpful but not absolutely essential.
Job Requirements:

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BS in EE/CS/Math. with 9+ years of relevant experience, MS with 7+ years of relevant experience, or related Ph.D.
It is essential that the individual has strong desires to learn and explore new technologies and are able to demonstrate
good analysis and problem solving skills. Prior knowledge and experience of CAD tool/EDA development are a big plus.




Job site:

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The researcher will be part of Atrenta's EU based advanced research center  and can work from any EU country.

The company will not sponsor immigration visa.





Contact Person

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Fahim at atrenta.com<https://mail.atrenta.com/owa/redir.aspx?C=50d5299bf38e40688a9d513a75efb11e&URL=mailto%3aFahim%40atrenta.com>






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