V22.0436 - Prof. Grishman

Lecture 22: Caches

Effect on performance

Line size and spatial locality

To take advantage of spatial locality, most caches use a line size of more than one word; for example, the Pentium uses 32-byte lines. To minimize delay in filling such a cache, modern processors provide a wide path from memory to processor, and the ability to stream data quickly from memory to processor. For example, the Pentium has a 64-bit data path into the processor.


Caches differ in how they handle stores: a write-through cache updates main memory (as well as the cache) as soon as a store is executed. A write-back cache updates only the cache; main memory is updated when the block is removed from the cache. (text, p. 607)

Two-level cache

Most systems now have two levels of cache: a very fast, small "level 1" cache inside the processor chip (e.g., 16-32KB) and a larger, somewhat slower "level 2" cache outside the chip (typically 256KB up to 1 MB). As processors get faster, any off-chip cache is going to be slower than the processor; the small, on-chip cache eliminates most of the delay waiting for the off-chip cache. (On the Pentium Pro and Pentiums II and III, the Level 2 cache is integrated into the same package with the processor.  The Pentium III has a 512KB L2 cache, and separate 16K L1 caches for instructions and data.)

Spring 1999