Operating Systems

================ Start Lecture #17 ================

Homework: 16, 8 (should have been assigned last time.

Comments on the Midterm exam and midterm grades

I graded the midterm exam. The grades ranged from 64-98, with a mean of 83.4 and median of 82. I was pleased to see that there were no failing exams. The breakdown was

90-99 16
80-89 12
70-79 16
60-69 2

The midterm grades were based on just lab1 and the midterm exam (lab2 had not yet been graded) with the midterm counting roughly 2 to 1, reflecting the fact that the final grade is roughly 2/3 exams 1/3 labs.

I only assign midterm grades of A B C C- D F For the final grades I of course use the full complement of +- grades (no C-) and look at homeworks for students just below a cutoff

I am pleased to say that there were no Fs.

10 students have not handed in the first lab (linker). They account for all 7 Ds and 3 of the four C-'s.

End of Comments

4.3: Virtual Memory (meaning fetch on demand)

Idea is that a program can execute even if only the active portion of its address space is memory resident. That is, swap in and swap out portions of a program. In a crude sense this can be called “automatic overlays”.



** 4.3.1: Paging (meaning demand paging)

Fetch pages from disk to memory when they are referenced, with a hope of getting the most actively used pages in memory.

Homework: 12.

4.3.2: Page tables

A discussion of page tables is also appropriate for (non-demand) paging, but the issues are more acute with demand paging since the tables can be much larger. Why?

  1. The total size of the active processes is no longer limited to the size of physical memory. Since the total size of the processes is greater, the total size of the page tables is greater and hence concerns over the size of the page table are more acute.

  2. With demand paging an important question is the choice of a victim page to page out. Data in the page table can be useful in this choice.

We must be able access to the page table very quickly since it is needed for every memory access.

Unfortunate laws of hardware.

So we can't just say, put the page table in fast processor registers, and let it be huge, and sell the system for $1000.

The simplest solution is to put the page table in main memory. However it seems to be both too slow and two big.

  1. Seems too slow since all memory references require two reference.
  2. The page table might be too big.

Contents of a PTE

Each page has a corresponding page table entry (PTE). The information in a PTE is for use by the hardware. Information set by and used by the OS is normally kept in other OS tables. The page table format is determined by the hardware so access routines are not portable. The following fields are often present.

  1. The valid bit. This tells if the page is currently loaded (i.e., is in a frame). If set, the frame pointer is valid. It is also called the presence or presence/absence bit. If a page is accessed with the valid bit zero, a page fault is generated by the hardware.

  2. The frame number. This is the main reason for the table. It gives the virtual to physical address translation.

  3. The Modified bit. Indicates that some part of the page has been written since it was loaded. This is needed if the page is evicted so that the OS can tell if the page must be written back to disk.

  4. The referenced bit. Indicates that some word in the page has been referenced. Used to select a victim: unreferenced pages make good victims by the locality property (discussed below).

  5. Protection bits. For example one can mark text pages as execute only. This requires that boundaries between regions with different protection are on page boundaries. Normally many consecutive (in logical address) pages have the same protection so many page protection bits are redundant. Protection is more naturally done with segmentation.

Multilevel page tables

Recall the previous diagram. Most of the virtual memory is the unused space between the data and stack regions. However, with demand paging this space does not waste real memory. But the single large page table does waste real memory. The idea of multi-level page tables (a similar idea is used in Unix i-node-based file systems, which we study later) is to add a level of indirection and have a page table containing pointers to page tables.

Address translation with a 2-level page table

For a two level page table the virtual address is divided into three pieces

| P#1 | P#2 | Offset|

Do an example on the board

The VAX used a 2-level page table structure, but with some wrinkles (see Tanenbaum for details).

Naturally, there is no need to stop at 2 levels. In fact the SPARC has 3 levels and the Motorola 68030 has 4 (and the number of bits of Virtual Address used for P#1, P#2, P#3, and P#4 can be varied).

4.3.3: TLBs--Translation Lookaside Buffers (and General Associative Memory)

Note: Tanenbaum suggests that “associative memory” and “translation lookaside buffer” are synonyms. This is wrong. Associative memory is a general concept and translation lookaside buffer is a special case.

An associative memory is a content addressable memory. That is you access the memory by giving the value of some field and the hardware searches all the records and returns the record whose field contains the requested value.

For example

Name  | Animal | Mood     | Color
Moris | Cat    | Finicky  | Grey
Fido  | Dog    | Friendly | Black
Izzy  | Iguana | Quiet    | Brown
Bud   | Frog   | Smashed  | Green
If the index field is Animal and Iguana is given, the associative memory returns
Izzy  | Iguana | Quiet    | Brown

A Translation Lookaside Buffer or TLB is an associate memory where the index field is the page number. The other fields include the frame number, dirty bit, valid bit, and others.

Homework: 17.