Simulated Toy Machine

Architecture for projects for Computer Systems Organization II, section 1.

The Simulated Toy Machine (STM) is a simulation of an extremely simple machine architecture, which we will use for programming assignments 1-3. These projects involve extending the operating system for this toy machine.

Warning: There is one very misleading aspect to this toy machine, as compared to real machines. Unlike any conceivable real operating system (and also unlike the Nachos simulated machine used in the honors section), the "operating system" for STM is not resident in the simulated machine; rather, it is part of the simulator. This is why, for instance, the STM does not need interrupts; in effect, control reverts to the "operating system" after every instruction. It is critical to keep this difference in mind when you try to relate your experiences in programming the STM to the running of real operating systems.

There are also, of course, numerous other unrealistic aspects to the STM; for instance, we make no attempt to model blocking a process for I/O.

Basic Architecture

The basic architecture of the STM contains That's it.

Machine language --- STML

Strictly speaking, there's actually no need for you to care about the structure of STML. You're not going to have to write code in STML, and the code to execute STML instructions is all provided for you. This is just here for the sake of concreteness. Each instruction in STML is a 32-bit word, organized as follows: (bits are numbered from low-order to high-order; thus bit 0 is the lowest order bit.)

The op codes are as follows:
Op code Abbreviation Args Meaning
0 LOA RA, AD Load the value at AD into RA
1 STO RA, AD Store the value at RA into AD
2 CPR RA, RB Copy RB into RA
3 LOI RA, RB RB holds the address of AD. Load the value of AD into RA.
4 STI RA, RB RA holds the address of AD. Store the value in RB into AD.
5 ADD RA, RB, RC RC = RA + RB
6 SUB RA, RB, RC RC = RA - RB
7 MUL RA, RB, RC RC = RA * RB
8 DIV RA, RB, RC, RD RC = RA / RB; RD = RA % RB.
9 ICR RA RA++
10 DCR RA RA--
11 GTR RA, RB, RC RC = (RA > RB)
12 JMP RA, AD Jump to AD. (RA is unused).
13 IFZ RA, AD If (RA == 0) then goto AD.
14 JMI RA RA holds the address of AD. Jump to AD.
15 TRP Trap to the kernel.

Note: The arithmetic operations are all integer. An instruction that has two or more identical register arguments may have unexpected results.

Thus, for example, the hexadecimal value 0x11B0 consists of the opcode 0, the register value 0xB == 11, and the address 0x11 = 17, so it indicates the instruction to load address 17 to register R11.

System calls

A user process executes a system call by executing an instruction of the form "TRP". The value of register R15 indicates the nature of the system call, as follows:

STML source files

A code file in STML has the following form: You may assume that the STML file is correctly formatted.

Basic STM interpreter

A basic STM interpreter for a single process is available in stm.c

The program is executed with the following command line:

stm* [-b BASE] [-d DEBUGGING-LEVEL] [-m MAX] sml-file
where The "-b", "-d", and "-m" flags may be given in any order; the file name must be the last argument on the line.

The execution of the STM follows the standard "fetch-execute" cycle:

Execution continues until either the process intentionally terminates, or aborts due to an error, or reaches the specified maximum number of instructions.

Address translation: The addresses in STML are all relative addresses. The base register holds the starting address of the process, and the physical address is equal to the relative address plus the base register. The limit register holds the size of the partition. Any relative address that is less than 0 or greater than or equal to the value of the limit register causes an error.

Errors: Any runtime error causes termination of the process. I think that the following list includes all possible runtime errors:

All these errors except overflow are caught by the STM interpreter, which exits smoothly. I am doubtful that there is any easy way to catch overflow errors that will work on all systems. Therefore, these are not intercepted, and will cause the STM interpreter to abort.