G22.2233 - Prof. Grishman

Lecture 8: MIPS Processor Design:  Single Cycle Control (cont'd)

How the single cycle CPU works

Note:  sequence reflects data flow ... everything happens in a single clock cycle.

for all instructions: fetch instruction from instruction memory

for R-type instructions:

for load: for store: for beq:

How fast?

For a synchronous machine, clock period must be greater than maximum propagation delay of combinational circuit (which computes next state (text, page B-40).  So the period for MIPS must be greater than time required for longest instruction.

Can we do better?  To answer that, we must consider

Measuring Performance

Text: Chapter 2

What is performance? Computer performance is a measure of how long it takes to perform a task, or how many tasks can be performed in a given time period. The performance that matters to us is how long it takes to perform our tasks. However, unless we can afford to benchmark our task on each machine we are considering, we have to rely on more generic measures of computer performance.

For the moment, we shall just discuss CPU performance and ignore IO. The basic equation is:

time to run program = (number of instructions executed) * (average CPI) * (clock cycle time)

where CPI = number of clock cycles per instruction. For a given program, the number of instructions executed depends on the compiler used and on the architecture (instruction set). The average CPI depends on the implementation of the architecture.

Some Popular Metrics

Improving Performance

Our goal is to minimize the product of the three factors given above. Each change must be judged on its overall effect.

MIPS Implementations: multiple clock cycles / instruction

Text: section 5.4

We can modify the design of the MIPS machine to use a faster clock (2 ns) and multiple clock cycles per instruction. In the design given in section 5.4, instructions require up to 5 clock cycles:

  1. instruction fetch (for all instructions)
  2. instruction decode and register fetch (for all instructions)
  3. ALU operation (for all instructions)
  4. for R-type instructions, register store; for lw/sw, data memory operation
  5. for lw, register store
This revised design enables a single memory to be used for instructions and data, but requires additional registers to hold the instruction and the data read from memory, as well as registers to hold the output of the register file and the ALU (Fig. 5.30, page 378).

Spring 2002