### Lecture 4: Logic Design -- Sequential Circuits

#### Representing sequential circuits (text, sec. B.6)

• a sequential circuit can be described as a finite state machine

• (text, section B.6)
• state machine includes a next-state function and an output function

• (text, figure B.27)
• next-state function can be represented by a graph or a table
• graph: finite state transition network
• transition table: table which gives new state as a function of current state and inputs
##### Finite state transition network
• a network consists of a set of nodes connected by arcs
• each node represents a state of the circuit (so a circuit with n bits of registers may have 2**n states)
• each arc represents a possible transition between states; it is labeled by the condition (if any) under which the transition is made
##### Transition table
In a transition table, the input columns represent the state of the circuit and the inputs to the circuit; the output columns represent the next state of the circuit.
##### Designing a sequential circuit
• (sometimes) draw a transition network for the circuit
• build a transition table
• use the transition table as the truth table for the "next state" combinatorial circuit
• convert this table to a circuit
• if necessary, build an output function truth table and convert it to a circuit
• example: binary up-counter; binary up-down counter
• example: "traffic light" circuit from text

### MIPS architecture

We will base our computer design on the MIPS architecture (text, chapter 3).  Its simple structure allows for relatively simple machine designs.
• 32 32-bit registers, referred to in assembly language as \$0 ... \$31, or by names indicating typical uses, such as \$s0 ... \$s7 (see Figure 3.13, p. 140 for a full list)
• use of register 0 (\$zero) as constant 0
• byte-addressable memory (word = 4 bytes)
• 32-bit instructions (see chart in text, endpaper)
• load-store architecture: arithmetic and logical operations operate on registers and store result in another register;  separate instructions for loading from / storing to memory  (lw and sw instructions for words, lbu and sb for bytes)
• uniform 2-operand arithmetic and logical instructions  (e.g.,  add  r1, r2, r3)
• a RISC (reduced instruction set) architecture
• two-instruction sequence for branch on less than (assembler provides single pseudoinstruction)
Sharp contract with CISC (complex instruction set) architectures such as the Intel 80x86 (sec. 3.12)
• historical requirements of upward compatibility with earlier machines led to complex design (8080 -> 8086 -> 80286 -> 80386 -> 80486 -> Pentium -> MMX etc.)
• almost every register has some special properties
• operands for instructions can come from memory or register; result can be stored to memory or register
• multiple operand sizes; multiple instruction lengths
• complex machine design