G22.2233 - Prof. Grishman

Assignment 2:  The MIPS ALU

The heart of the MIPS processor is its ALU (arithmetic-logic unit).  For this assignment, you will implement (using our logic simulator) a scaled-down version of the ALU, with 6-bit operands and a 6-bit result.  We will later use this as part of a complete MIPS CPU.

The design should follow that described in pages 230 to 241 of the text.  The final circuit, as shown in Figure 4.19, should have two 6-bit inputs a and b as well as inputs op0, op1, and Bnegate;  it should have a 6-bit result output as well as individual wires zero, carryOut, and overflow.

You should define a class ALU with constructor

ALU (Bus result, Wire zero, Wire carryOut, Wire overflow, Bus a, Bus b,
     Wire Bnegate, Wire op1, Wire op0)
Be sure to follow this order for arguments!  Wire op0 corresponds to the low-order bit in the ALU control lines (Figure 4.20), op1 to the middle bit, and Bnegate to the high order bit.  So, for example, an add is performed by setting op1=1 and having the other two bits 0.  You are also free to define other classes which you use in building the ALU.  In particular you may want to build a 1-bit ALU slice, and a circuit for the high bit, following Figure 4.17.

Compute the (maximum) propagation delay time of your ALU.  Give a sequence of inputs which require this maximum delay time before the output is correct.

You should send email to grishman@cs.nyu.edu which contains a single attachment containing the definitions of the ALU class, and any other classes you used in defining the ALU. (It should not contain a main method.)  Place the answer to the question about propagation delay in the body of the message.  The subject line of the message should be "Assignment 2".  It will be easier for me if the attachment file name is yourname.java.

This assignment is due March 18th, and is worth 7 points towards your final grade.  There is a penalty of 1/2 point for each school day the assignment is late.

Simulator for Assignment 2:  This is an upgrade of the simulator, which includes additional primitive gates (Not, And2, Or2, Xor2, Mpxr2, and FullAdder) and support for busses (arrays of wires). Upgrade documentationJava code (release 2.0).