V22.0436 - Prof. Grishman

Lecture 24: Cache (concluded); Input-Output

Cache -- final notes

To take advantage of spatial locality, most caches use a line size of more than one word; for example, the Pentium uses 32-byte lines. To minimize delay in filling such a cache, modern processors provide a wide path from memory to processor, and the ability to stream data quickly from memory to processor. For example, the Pentium has a 64-bit data path into the processor.

Caches differ in how they handle stores: a write-through cache updates main memory (as well as the cache) as soon as a store is executed. A write-back cache updates only the cache; main memory is updated when the block is removed from the cache.

Most systems now have two levels of cache: a very fast, small "level 1" cache inside the processor chip (e.g., 16-32KB) and a larger, somewhat slower "level 2" cache outside the chip (typically 256KB up to 1 MB). As processors get faster, any off-chip cache is going to be slower than the processor; the small, on-chip cache eliminates most of the delay waiting for the off-chip cache. (On the Pentium Pro and Pentium II, the Level 2 cache is integrated into the same package with the processor.)

Virtual memory

Virtual memory provides the next step in the memory hierarchy after main memory: disk memory. The gap in access times, however, is much larger (between 100ns main memory and 10ms disk access time) and this affects the parameters of the design (pages are much larger than cache lines, and hit ratios must be much higher for the machine to work efficiently). As technology changes, we can expect the parameters of the memory levels to change, but the basic idea of a memory hierarchy to remain.


Input-output: needs

Input-output: bus organization