V22.0436 - Prof. Grishman

Lecture 11: MIPS Processor Design: Building a Datapath

Text: Section 5.2

we will limit ourselves to a few instructions: lw, sw, beq, add, sub, and, or, slt

for simplicity in our initial design, we will assume separate memories for instructions and data; this will allow us to create a design which can read an instruction and then read or write data in a single cycle (text, Fig. 5.1)

Basic components

Building the data paths for the simple (single-cycle) implementation scheme (Fig. 5.5- 5.11)