V22.0436 - Prof. Grishman

Assignment 4 - Simulating the MIPS CPU

Write a procedure to simulate a MIPS CPU as developed in Chapter 5.3 of the text, and which implements the add, sub, and, or, slt, lw, sw, and beq instructions. In general, have the modules of your simulation program correspond to the modules of the CPU circuit. Include some comments on each procedure to explain their relationship to the design in the text (figure 5.22).

The procedure for the CPU will invoke the procedures for the different modules (instruction memory, control, ALU control, register file, etc.) in the order in which signals are propagated to execute an instruction. However, the register file modules will have to be invoked twice --- first for register reads, and at the end for register writes.

In general, the code should not have if ... then ... else ... or case constructs: as in previous assignments, everything should be done by logical operations. However, you do not need to simulate the internal structure of the registers or memories; the register file and memories may be simulated in any way that is convenient, typically using an array to hold the memory or register values. Also, you need to simulate only as large a memory as you need for testing.

Implement a main program and set of test programs+data which systematically tests the CPU. For each test, your main program will initialize the program and data memories, the registers and PC, and then simulate instructions until some stopping condition is reached. Since we have not included a stop instruction, you may set some arbitrary stopping condition, such as having the program jump to 1000.

You may need to create several test programs to thoroughly test the CPU design. Document the testing procedure, showing how all significant paths and cases have been tested.

Submit a program listing and test output. A good test output will show an instruction-by-instruction trace of the program execution.

For extra credit: extend you design to handle the addi instruction.

Due November 24. Late assignments are penalized 10% for each weekday late.