### Lecture 3:   Logic Design -- Simulation;  combinational Circuits:  propagation delay

#### Circuit simulation

• old-fashioned approach:  breadboarding ... build and test
• difficult even for systems using off-the-shelf parts
• importance of simulating designs before they are built
• simulation becomes much more important for VLSI
• tooling up to build a new VLSI circuit is very expensive
• (low cost is obtained by making a large number of a single design)
• hard to debug a circuit once it is built
• distributing a chip (processor) with a bug can cause huge problems
• special purpose simulators for logic simulation
• two approaches to circuit entry:
• specialized languages:  VHDL, Verilog
• graphical entry of circuits
• we will use a graphical entry approach:  Logisim

#### Propagation delay (note: not covered in text)

• delay of individual transistor -- how fast it can switch -- determined by physical factors (e.g., size)
• speed of transistor determines speed of gate
• the propagation delay (speed) of a combinatorial circuit is the length of time from the moment when all input signals are stable until the moment when all outputs have stabilized
• propagation delay of a combinatorial circuit can be determined as longest path (in number of gates) from any input to any output

#### Fan-in (note: not covered in text)

• sum-of-products form suggests any combinatorial function can be computed in 3 gate delays (one delay for inverters, one for ANDs, one for OR)
• but gates are limited in their fan-in (number of inputs a gate has)
• so, for example, if fan-in is f, it takes log (base f) n gate delays to OR or AND together n inputs

#### Ripple carry adder (C-26 to 28;  C-46)

• simplest n-bit binary adder connects together n full adders, feeding Cout of bit k into Cin of bit k+1 (where low order bit is bit 0)
• delay is approximately n * delay(Cin,Cout) of full adder

#### Representing signed numbers (text, section 2.4 and 3.2)

• negative numbers generally represented in two's complement
• computing the two's complement:  flipping each bit and adding 1
• doing subtraction by adding the two's complement
(simple subtractor using one row of full adders:  page C-30)