CSCI-UA.0436 - Prof. Grishman

Lecture 14: MIPS Processor Design: Single Cycle Control

A simulator for the single-cycle MIPS machine, PathSim, is available from St. Bonaventure University.
(A older version which runs under earlier versions of Java is available here.)

Control Logic

We must construct logic to control the ALU functions plus the following control lines (see Fig. 4.16): MemRead, MemWrite, ALUSrc, RegDst, RegWrite, PCSrc, and MemtoReg. We construct a truth table in which the inputs are the instruction --- specifically, the opcode and function fields --- and the outputs are the control signals and ALU function. P&H do this in two steps: The control signals (exclusive of ALU function) are determined by the opcode alone. The dependence is shown in Figure 4.18. P&H then define a two-bit signal called ALUOp, which is a function of the opcode. The ALU control signal truth table is then based on two inputs: ALUOp and the function field (Figure 4.13).

Building the Control Unit

We then have to convert these two truth tables to combinational logic.  P&H do this in Appendix D, section 2.  For the main control unit, we use standard sum-of-products logic.  The full truth table, with opcode inputs and control signal outputs, is shown in Figure 4.22.  The resulting circuit is shown in Figure D.2.5.  For the ALU control unit, we take advantage of the don't cares in the truth table to produce a simple circuit, shown in Figure D.2.3.

Combining these circuits with the data path produces a complete computer (Figure 4.17).

How the single cycle CPU works (pages 321-326)

Sequence reflects data flow ... everything happens in a single clock cycle.

for all instructions: fetch instruction from instruction memory

for R-type instructions:

for load: for store: for beq: