V22.0436 - Prof. Grishman

Assignment 6:   MIPS Control Unit

In this assignment you will use Logisim to build two separate circutis, the main control and the ALU control for the single-cycle MIPS processor covered in class and described in chapter 4.  The hardware designs are shown in Appendix D.

The ALU control should have as inputs (from top to bottom) a two-wire bundle,  ALUOp, and a 6-wire bundle, Func.  Its output should be a 4-wire bundle, ALUcon.

The main control unit should have as input the opcode, a 6-bit bundle, Op.  The outputs should be (from top to bottom):  branch, RegDst, MemRead, MemToReg, ALUOp, MemWrite, ALUSrc, and RegWrite. ALUOp is a 2-wire bundle;  the rest are all single wires.

For extra credit, add the logic for the nor instruction to the ALU control.  Note that the logic in the book is carefully optimized for the selected instructions, so adding nor  may require some redesign of the circuit, not just adding gates.  For the extra credit, it is not required that the design be as optimized as the P&H design.

Due Thursday, November 4th.

Mail your homework (the .circ file) to  grishman@cs.nyu.edu and chanseok@cs.nyu.edu and mark the mail CompArch -- Asgn 6.  If you have included the extra credit, say so in the mail.