V22.0436 - Prof. Grishman

Lecture 15: MIPS Processor Design: Single Cycle Control (cont'd)

A simulator for the single-cycle MIPS machine, PathSim, is available from St. Bonaventure University.
(A older version which runs under earlier versions of Java is available here.)

How the single cycle CPU works (pages 321-326)

Sequence reflects data flow ... everything happens in a single clock cycle.

for all instructions: fetch instruction from instruction memory

for R-type instructions:

for load: for store: for beq:

How fast?

For a synchronous machine, clock period must be greater than maximum propagation delay of combinational circuit (which computes next state).  So period for MIPS must be greater than time required for longest instruction.

How long is that?  Assume memories and ALU have 200 ps delay, and the register file (for read or write) 100 ps delay.  (Text, pp. 332-333)

Can we do better?  To answer that, we must consider

Measuring Performance

Text: Section 1.4

What is performance? Computer performance is a measure of how long it takes to perform a task, or how many tasks can be performed in a given time period. The performance that matters to us is how long it takes to perform our tasks. However, unless we can afford to benchmark our task on each machine we are considering, we have to rely on more generic measures of computer performance.

For the moment, we shall just discuss CPU performance and ignore IO. The basic equation is:

time to run program = (number of instructions executed) * (average CPI) * (clock cycle time)

where CPI = number of clock cycles per instruction. For a given program, the number of instructions executed depends on the compiler used and on the architecture (instruction set). The average CPI depends on the implementation of the architecture.

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