Computer Architecture

Start Lecture #21

Remark: Demo of tristate drivers in logisim (controlled registers).

Improvement: Multiword Blocks

The setup we have described does not take any advantage of spatial locality. The idea of having a multiword block size is to bring into the cache words near the referenced word since, by spatial locality, they are likely to be referenced in the near future.

We continue to assume (for a while) that the cache is direct mapped and that all references are for one word.

The terminology for byte offset and block offset is inconsistent. The byte offset gives the offset of the byte within the word so the offset of the word within the block should be called the word offset, but alas it is not in both the 2e and 3e. I don't know if this is standard (poor) terminology or a long standing typo in both editions.

The figure to the right shows a 64KB direct mapped cache with 4-word blocks.

What addresses in memory are in the block and where in the cache do they go?

Show from the diagram how this gives the red portion for the tag and the green portion for the index or cache block number.

Consider the cache shown in the diagram above and a reference to word 17003.

The cache size is the size of the data portion of the cache (normally measured in bytes).

For the caches we have see so far this is the Blocksize times the number of entries. For the diagram above this is 64KB. For the simpler direct mapped caches blocksize = wordsize so the cache size is the wordsize times the number of entries.

Let's compare the pictured cache with another one containing 64KB of data, but with one word blocks.

  1. Calculate on the board the total number of bits in each cache; this is not simply 8 times the cache size in bytes.
  2. If the references are strictly sequential the pictured cache has 75% hits; the simpler cache with one word blocks has no hits.

How do we process read/write hits/misses for a cache with multiword blocks?

Homework: 7.9, 7.10, 7.12.

Why not make blocksize enormous? For example, why not have the cache be one huge block.

Memory support for wider blocks

Recall that our processor fetches one word at a time and our memory produces one word per request. With a large blocksize cache the processor still requests one word and the cache responds with one word. However the cache requests a multiword block from memory and to date our memory is only able to respond with a single word.

The question is, "Which pieces and buses should be narrow (one word) and which ones should be wide (a full block)?". The same question arises when the cache requests that the memory store a block and the answers are the same so we will only consider the case of reading the memory).

Homework: 7.14