Computer Architecture

Start Lecture #10

I-type (Immediate)

The I is for immediate.

Load Word and Store Word

Examples: lw/sw $1,1000($2)

RISC-like properties of the MIPS architecture.

addi (add immediate)

Example: addi $1,$2,100

2.5: Logical Operations

Shifts: sll and srl (shift left/right) logical

Examples sll/srl $8,$12,7

Bitwise AND and OR: and, or, andi, ori

No surprises.

Bitwise NOR (includes NOT): nor

MIPS includes a bitwise NOR (our ALU implemented it) implemented as an R-type instruction.

2.6: Instructions for Making Decisions

beq and bne (branch (not) equal)

Examples: beq/bne $1,$2,123

slt (set less-then)

Example: slt $3,$8,$2

slti (set less-then immediate)

Example: slt $3,$8,20

blt (branch if less than)

Example: blt $5,$8,123

ble (branch if less than or equal)

Example: ble $5,$8,L (L a label to be calculated by the assembler.)

bgt (branch if greater than)

Example bgt $5,$8,L

bge (branch if greater than or equal)

Example: bge $5,$8,L

Note: Please do not make the mistake of thinking that
  stl $1,$5,$8
  beq $1,$0,L
is the same as
  stl $1,$8,$5
  bne $1,$0,L

It is not the case that the negation of X < Y is Y > X.
End of Note

J-type instructions (J for jump)

These have a different format, but again the opcode is the first 6 bits.
  op address
  6   26

The effect is to jump to the specified (immediate) address. Note that there are no registers specified in this instruction and that the target address is not relative to (i.e. added to) the address of the current instruction as was done with branches.

j (jump)

Example: j 10000

But MIPS is a 32-bit machine with 32-bit address and we have specified only 26 bits. What about the other 6 bits?

In detail the address of the next instruction is calculated via a multi-step process.

  1. The 26 bit address field is extracted from the instruction.
  2. This address is left shifted two bits. The result is a 28-bit address (call it A) that is always a multiple of 4, which makes sense since all instructions must begin on a multiple of 4 bytes.
  3. The high order 4 bits are extracted from the address of the current instruction (not the address in the current instruction). Call this 4-bit quantity B.
  4. The address of the next instruction is formed by concatenating B with A.

2.7: Supporting Procedures in Computer Hardware

jal (jump and link)

Example: jal 10000

jr (jump register)

Important example: jr $31

Homework: 2.38

2.8: Communicating with People


MIPS Addressing for 32-bit Immediates and Addresses

How can we put a 32-bit value (say 2 billion) into register 6?

  1. Zero and add.
  2. Load the word
  3. Load shift add
  4. Load shift OR

lui (load upper immediate)

Example: lui $4,123

Homework: 2.29 (assume b≥0), 2.7, 2.32, 2.33.