Computer Architecture

Start Lecture #8

Registers

A register is basically just an array of D flip-flops. For example a 32-bit register is an array of 32 D flops.

• What if we don't want to write the register during a particular cycle (i.e. at the active edge of a particular cycle)
• Introduce another input, the write line.
• The write line is used to gate the clock.
• Clearly if the write line is high forever, the clock input to the register is passed right along to the D flop and hence the input to the register is stored in the D flop when the active edge occurs (for us the falling edge).
• Also clear is that if the write line is low forever, the clock to the D flop is always low so has no edges and no writing occurs.
• Now we understand what happens if the write line never changes. What if we want to change the write line (i.e., assert or de-assert it)?
• Assert or deassert the write line while the clock is low. Changing the Write line when the clock is low has no effect on the output of the AND and hence does not effect the clock to the D flop. In particular it does not introduce any new edges.
• So we change the write line only when the clock is low.

This, however, is not so good! We must have the write line correct quite a while before the active edge. That is you must know whether you are writing quite a while in advance.

• Better to arrange everything so that the write line must be correct when the clock is high (i.e., just before the active edge).
• Thus we OR the write line with the clock so that it can be changed when the clock is high without affecting the clock to the D-flop.

An alternative is to use an active low write line, i.e. have a W' input.

To implement a multibit register, just use multiple D flops.

• Note that the 3-bit Data input is shown both as one 3-bit line and as three 1-bit lines.
• This dual representation is also used for the 3-bit Out line.

Register File

A register file is just a set of registers, each one numbered.

• To access a register file, you supply the register number, the write line (asserted if a write is to be done), and, if the write line is asserted, the data to be written. write).
• You can read and write same register during one cycle. You read the old value and then the written value replaces this old value for subsequent cycles.
• Often have several read and write ports so that several registers can be read and written during one cycle.
• We will implement 2 read ports and one write port since that is needed for ALU ops. This is Not adequate for superscalar (or EPIC) or any other system where more than one operation is to be calculated each cycle.

To support reading a register we just need a (big) mux from the register file to select the correct register.

• Use one big mux for each read port.
• A big mux means an n-input, b-bit mux, where
• n is the number of registers (32 for MIPS)
• b is the width of each register (32 for MIPS)
• As always we need ceiling(log(n)) bits for selecting which of the n input to produce.

Writing a Register in a Register File

To support writing a register we use a decoder on the register number to determine which register to write. Note that errors in the book's figure were fixed.

1. The decoder is log n to n (5 to 32 for MIPS).
2. The decoder outputs are numbered 0 to n-1 (NOT n).

Note also that I show the clock explicitly.

Recall that the inputs to a register are W, the write line, D the data to write (if the write line is asserted), and the clock. We should perform a write to register r this cycle if the write line is asserted and the register number specified is r. The idea is to gate the write line with the output of the decoder.

• The clock to each register is simply the clock input to the register file.
• The data to each register is simply the write data to the register file.
• The write line to each register is unique.
• The register number is fed to a decoder.
• The rth output of the decoder is asserted if r is the specified register.
• Hence we wish to write register r if
• The write line to the register file is asserted
• The rth output of the decoder is asserted
• Bingo! We just need an and gate.