### Practice Final Exam Questions

#### Time calculations

1. A processor runs at 2GHz. What is the length of its clock cycle? (Give your answer in microseconds, nanoseconds, or picoseconds.)
2. A disk has an access time of 10 ms. Assuming the time for data transfer is negligible, how many disk accesses can be performed each second?
3. A disk rotates at 6000 RPM.  What is its average rotational latency?
4. The access time of a disk is composed of ______________ and _____________.
5. Suppose we have a loop of 10 machine instructions and we execute this loop one billion times on a 2 GHz machine with a CPI of 2.0.  How long will the billion iterations of the loop take?

#### Combinational Circuits

1. Design a fast circuit to compute the sum of two 2-bit positive numbers. Construct a truth table for such a circuit, and then convert the truth table into a sum-of-products logic formula for each output. What is the propagation delay of this circuit, from input to output?

#### Sequential Circuits

1. Given D-type master-slave or edge-triggered FFs, AND, OR, NAND, NOR gates, inverters, and multiplexers, design a 4-word, 2 bit per word register file with a single input port and a single output port.

#### MIPS Processor Design

1. Write a MIPS program with a loop which copies the 20 words (80 bytes) beginning at byte 1000 to the 20 words beginning at byte 2000.
2. What is the purpose of the 'sign extend' circuit in the MIPS CPU you simulated? Suppose we didn't have a sign extend circuit; what limitation would there be on branch instructions?
3. Is it possible for a program to modify its instructions in the single cycle MIPS CPU? in the multi-cycle CPU?

#### Processor Performance and Pipelining

1. Suppose that when program Zippo runs, it executes 200,000 loads, 100,000 stores, 699,998 R-type instructions, and 2 multiply instructions. Consider 2 machine designs: in design M1, the clock rate is 100Mhz; loads and stores take 2 cycles, R-type instructions take 1 cycle, and multiplies take 5 cycles. In design M2, the clock rate is 66Mhz and all instructions take 1 cycle. Which machine is faster?
2. On a pipelined MIPS machine, the instruction sequence