G22.2243-001 (Fall 2002)
High Performance Computer Architecture

Course Description

 

General Information

Instructor:

Vijay Karamcheti (vijayk@cs.nyu.edu), 
715 Broadway, Room 704; phone: 8-3496

Lectures:

Wednesdays: 5:00pm 7:00pm
101 CIWW

Office Hours:

Tuesdays: 4:00pm 5:00pm
715 Broadway, Room 704

Mailing List:

To subscribe, follow instructions at 
     http://www.cs.nyu.edu/mailman/listinfo/g22_2243_001_fa02

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     g22_2243_001_fa02@cs.nyu.edu

Web Page:

http://www.cs.nyu.edu/courses/fall02/G22.2243-001/index.htm
All course materials, lecture slides, and announcements will be available here.

Prerequisites

Undergraduate- or graduate-level introductory course in computer architecture.

Description

This is a graduate-level course in computer architecture, focusing on a quantitative analysis of techniques that define current-day high-performance microprocessors. The main focus of the course will be on techniques at the micro-architecture level pipelining, static and dynamic exploitation of instruction-level parallelism, and efficient multi-level memory hierarchies. We shall also briefly discuss multithreaded and multiprocessor architectures, and storage and I/O networks. The latter topics are covered in additional detail in follow on courses, e.g., Architecture and Programming of Parallel Computers.

This is NOT an introductory computer architecture course. It is expected that students would have taken an earlier course at the level of V22.0436: Computer Architecture either at the undergraduate or graduate level. Students who do not meet this requirement are strongly encouraged to meet the instructor before they register for the course.

Textbook

         John L. Hennessy and David A. Patterson,
Computer Architecture: A Quantitative Approach, Third Edition,

Morgan Kaufmann, May 2002.

Course Structure

The course will consist of lectures based on material from the textbook supplemented with current research papers as appropriate.

There will be five programming and analysis assignments, during the course of which students will build, in stages, a timing simulator for a simplified out-of-order issue superscalar processor. These programming assignments will make use of the SimpleScalar toolkit (http://www.simplescalar.com). The assignments being used in this course were originally developed by Michele Co and Professor Kevin Skadron of the Computer Science Department at the University of Virginia.

In addition, there will be optional written assignments, drawn from exercises at the end of each chapter in the textbook. These assignments need not be handed in and are mainly intended to provide practice questions for the final exam.

The course grade will be computed as follows: programming and analysis assignments (60%), final exam (40%).