Arrays of Logic Elements

• Do the same thing to many signals
• Draw thicker lines and use the ``by n'' notation.
• Diagram below shows a 32-bit 2-way mux and an implementation with 32 1-bit, 2-way muxes.
• A Bus is a collection of data lines treated as a single logical (n-bit) value.
• Use an array of logic elements to process a bus. For example, the above mux switches between 2 32-bit buses.

Sequential Circuits, Memory, and State

Why do we want to have state?

• Memory (i.e., ram not just rom or prom)
• Counters
• Reducing gate count
  • Multiplier would be quadradic in comb logic.
  • With sequential logic (state) can do in linear.
    • What follows is unofficial (i.e. too fast to understand)
    • Shift register holds partial sum
    • Real slick is to share this shift reg with multiplier
    • We will do this circuit later in the course

B.4: Clocks

Assume you have a real OR gate. Assume the two inputs are both zero for an hour. At time t one input becomes 1. The output will OSCILLATE for a while before settling on exactly 1. We want to be sure we don't look at the answer before its ready.

Frequency and period

• Hertz (Hz), Megahertz, Gigahertz vs. Seconds, Microseconds, Nanoseconds
• Old (descriptive) name for Hz is cycles per second (CPS)
• Rate vs. Time

Edges

• Rising Edge; falling edge
• We use edge-triggered logic
• State changes occur only on a clock edge
• Will explain later what this really means
• One edge is called the Active edge
  • The edge (rising or falling) on which changes occur.
  • Choice is technology dependent.
  • Sometimes trigger on both edges (e.g., RAMBUS or DDR memory), but not in this course.

Synchronous system

Now we are going to add state elements to the combinational circuits we have been using previously.

Remember that a combinational/combinatorial circuits has its outpus determined solely by its input, i.e. combinatorial circuits do not contain state.

State elements include state (naturally).

• That is state elements are memory.
• State elements have clock as an input.
• These elements change state only at the active edge of the clock.
• They Always produce output, which is based on the current state.
• All signals that are written to state elements must be valid at the time of the active edge.
• For example, if cycle time (of the clock) is 10ns, the designer must ensure that combinational circuit used to compute new state values completes in 10ns.
• So state elements change at the active edge, the combinatorial circuit stabilizes between active edges.

Combinatorial circuits can NOT contain loops. For example imagine an inverter with its output connected to its input. So if the input is false, the output becomes true. But this output is wired to the input, which is now true. Thus the output becomes false, which is the new input. So the output becomes true ... .
However sequential circuits CAN and often do contains loops.

• Think of state elements as registers or memory.
• Can have loops like at the right.
• For example imagine the assembler instruction
  add-register r1=r1+r1
  The state element is register number 1 and the combinatorial circuit is a full adder.

B.5: Memory Elements

We will use only edge-triggered clocked memory in our designs as they are the simplest memory to understand. Our current goal is to construct edge-triggered clocked memory. However we get there in three stages.

1. We first show how to build unclocked memory.
2. Then, using unclocked memory, we build level-sensitive clocked memory.
3. Finally from level-sensitive clocked memory we build edge-triggered clocked memory.

Unclocked Memory

S-R latch (set-reset)

• ``Cross-coupled'' nor gates.
• Don't assert both S and R at once.
• When S is asserted (i.e., S=1 and R=0):
  • The latch is Set (that's why it is called S).
  • Q becomes true (Q is the output of the latch).
  • Q' becomes false (Q' is the complemented output).
• When R is asserted:
  • the latch is Reset.
  • Q becomes false.
  • Q' becomes true.
• When neither one is asserted:
  • The latch remains the same, i.e. Q and Q' stay as they were
  • This last statement is the memory aspect.

Clocked Memory: Flip-flops and latches

The S-R latch defined above is not clocked memory; unfortunately the terminology is not perfect.

For both flip-flops and latches the output equals the value stored in the structure. Both have an input and an output (and the complemented output) and a clock input as well. The clock determines when the internal value is set to the current input. For a latch, the output can change whenever the clock is asserted (level sensitive). For a flip-flop, changes occur only at the active edge.

D latch

The D is for data

• The left part uses the clock.
  • When the clock is low, both R and S are forced low so the outputs (Q and Q') don't change.
  • When the clock is high, S=D and R=D' so the value stored is D and the output is D.
• The output changes when input changes and the clock is asserted.
• Level sensitive rather than edge triggered.
• Sometimes called a transparent latch.
• We won't use these in designs.
• The right hand part of the circuit is the S-R (unclocked) latch we just constructed.
• The lower diagram (without the ``insides'') is how a D-latch is normally drawn.

D or Master-Slave Flip-flop

This was our goal. We now have an edge-triggered, clocked memory.

• Built from D latches, which are transparent.
• The result is Not transparent
  • Changes on the active edge.
  • This one has the falling edge as active edge.
• Sometimes called a master-slave flip-flop.
• Note substructures with letters reused having different meaning (block structure a la algol).
• Master latch (the left one) is set during the time, the clock is asserted. Remember that the latch is transparent, i.e. it follows its input when its clock is asserted. But the second latch is ignoring its input at this time. When the clock falls, the 2nd latch pays attention and the first latch keeps producing whatever D was at fall-time.
• Actually D must remain constant for some time around the active edge.
  • The set-up time before the edge.
  • The hold time after the edge.
  • See the discussion and diagram below.