### Lecture 5: Logic Design -- Simulation (cont'd);  Latches and Flip-Flops

Text: Appendix B.4 to 7

#### Principles of writing programs to simulate circuits

• each signal variable represents one signal (wire): has value 0 or 1
• expressions which compute these signal variables use only Boolean operations

• (in C, & [AND], | [inclusive OR], ^ [exclusive OR], and ~ [NOT])
• no conditional assignment: each variable is always assigned the same Boolean function of inputs and other variables
• single assignment: each variable is only assigned a value once in the process of computing a set of output values (no cycles in the combinational circuit)
• busses (sets of signal wires) represented by arrays

(discuss Assignment #2)

#### Combinational vs. sequential circuits

• in a combinational circuit, output (after some delay) is a function of inputs
• in contrast, a sequential circuit holds state information: the output is a function of the state of the device, as well as its inputs; in other words, sequential circuits have memory

#### Simple latches

• RS latch (reset-set latch): set and reset inputs (text, figure B.12)
• D-type latch: clock and data inputs (text, figure B.13): use of clock to control when a latch is updated
• register: set of latches with a common clock

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Spring 1999