### Lecture 4: Logic Design -- Fan-in; Addition and Subtraction;  Simulation

(discuss propagation delays from lecture 3 notes)

#### Fan-in (note: not covered in text)

• sum-of-products form suggests any combinatorial function can be computed in 3 gate delays (one delay for inverters, one for ANDs, one for OR)
• but gates are limited in their fan-in (number of inputs a gate has)
• so, for example, if fan-in is f, it takes log (base f) n gate delays to OR or AND together n inputs

#### Ripple carry adder (text, section 4.5, p. 232-235)

• simplest n-bit binary adder connects together n full adders, feeding Cout of bit k into Cin of bit k+1 (where low order bit is bit 0)
• delay is approximately n * delay(Cin,Cout) of full adder

#### Representing signed numbers (text, section 4.2)

• negative numbers generally represented in two's complement
• computing the two's complement:  flipping each bit and adding 1
• doing subtraction by adding the two's complement

#### Circuit simulation

• importance of simulating designs before they are built
• tooling up to build a new VLSI circuit is very expensive

• (low cost is obtained by making a large number of a single design)
• hard to debug a circuit once it is built
• distributing a chip (processor) with a bug can cause huge problems
• special purpose simulators ... operate from logic diagrams
• alternative: write programs (in C, Fortran, Pascal, ...) which mimic the operation of circuits

•

Spring 1999