Also, suppose that we have a processor where the CPI without cache misses is 1.2, that the instruction miss rate is 2%, the data fetch miss rate is 4%, and one half of the instructions contain a data fetch. Suppose the cache miss penalty is 7 cycles. What is the CPI if cache misses are taken into account?
Due April 28. Late assignments are penalized 5% after noon, 10% for each weekday late.