we will limit ourselves to a few instructions: lw, sw, beq, add, sub, and, or, slt
for simplicity in our initial design, we will assume separate memories for instructions and data; this will allow us to create a design which can read an instruction and then read or write data in a single cycle (text, Fig. 5.1)
The instructions we are considering (lw, sw, beq, add, sub, and, or, slt) are stored in three instruction formats (Fig. 5.16). The opcode of the instruction is stored in the high 6 bits (bits 26 to 31). However, the R-type instructions all are assigned opcode 0, and are differentiated by the "function" field, bits 0 to 5 of the instruction.
The register numbers are stored in the same place in all these instructions, and so we can connect the instruction fields (the output of the instruction memory) directly to the register number inputs on the register file. We need one multiplexer, however, since the number of the register to write sometimes appears in the rd field, bits 11 to 15 (for R-type instructions) and sometimes in the rt field, bits 16 to 20 (for load instructions). This produces the circuit shown in Fig. 5.17.
We construct a truth table in which the inputs are the instruction --- specifically, the opcode and function fields --- and the outputs are the control signals and ALU function. P&H do this in two steps: The control signals (exclusive of ALU function) are determined by the opcode alone. The dependence is shown in Figure 5.20. P&H then define a two-bit signal called ALUOp, which is a function of the opcode. The ALU control signal truth table is then based on two inputs: ALUOp and the function field (Figure 5.15).