### G22.2233 - Prof. Grishman

Final Exam:  Monday, May 13th, 5:00 - 6:50, Room 102 Warren Weaver Hall (not the regular classroom)

It will be an open book exam.  It will cover all the material from the course, although the emphasis will be on material since the mid-term (CPU design, performance analysis, cache, and IO).

### Practice Final Exam Questions

#### Time calculations

1. A processor runs at 100 Mhz. What is the length of its clock cycle?
2. A disk has an access time of 10 ms. Assuming the time for data transfer is negligible, how many disk accesses can be performed each second?

#### Combinational Circuits

1. Design a fast circuit to compute the sum of two 2-bit positive numbers. Construct a truth table for such a circuit, and then convert the truth table into a sum-of-products logic formula for each output. What is the propagation delay of this circuit, from input to output?

#### Sequential Circuits

1. Given D-type master-slave FFs, AND, OR, NAND, NOR gates, inverters, and multiplexers, design a 4-word, 2 bit per word register file with a single input port and a single output port.

#### MIPS Processor Design

1. Write a MIPS program with a loop which copies the 20 words (80 bytes) beginning at byte 1000 to the 20 words beginning at byte 2000.
2. What is the purpose of the 'sign extend' circuit in the MIPS CPU you simulated? Suppose we didn't have a sign extend circuit; what limitation would there be on branch instructions?
3. Is it possible for a program to modify its instructions in the single cycle MIPS CPU? in the multi-cycle CPU?
We may also ask you to make a small change in the MIPS CPU design, like you did for homework question 5.12 (see 5.5 to 5.11 for similar questions).

#### Processor Performance

1. Suppose that when program Zippo runs, it executes 200,000 loads, 100,000 stores, 699,998 R-type instructions, and 2 multiply instructions. Consider 2 machine designs: in design M1, the clock rate is 100Mhz; loads and stores take 2 cycles, R-type instructions take 1 cycle, and multiplies take 5 cycles. In design M2, the clock rate is 66Mhz and all instructions take 1 cycle. Which machine is faster?

#### Memory

1. Consider two alternative caches, each of which has a capacity of 8 words and a block size of one word. Cache D is a direct mapped cache, and cache T is a two-way set associative cache. Suppose the cache is initially empty and we fetch the words at the following addresses in sequence: 1, 2, 9, 3, 1, 5, 9. Which of these fetches will result in cache hits?
2. Suppose that we have a 10 ns cache (it takes 10 ns to access the data or identify a miss), and a memory system with a 100 ns access time. What is the average memory access time if the cache hit rate is 97%? If we built a larger cache, with a 12 ns access time but a hit rate of 98%, would the average memory access time increase or decrease?

#### IO

1. Suppose we have a floppy disk which transfers 50 KB and interrupts the CPU each time a byte is available. The CPU executes approximately 50 mips, and the interrupt routine takes 25 instructions to transfer a byte to memory. What fraction of the CPU time will be occupied doing IO with the floppy disk?
2. Consider a handshaking circuit for asynchronous data transmission, where the transmitter sets and resets a DATA READY signal, and the receiver sets and resets an ACKNOWLEDGE signal. Why must the receiver wait for ACKNOWLEDGE to be reset to 0 before commencing the transmission of the next bit? Indicate what could go wrong if it didn't.