CPU (Wire clock)There will be one difference from the MIPS design shown in the text. The memory we are providing is word addressable, not byte addressable, so you should design your CPU so that successive instructions are at addresses 0, 1, 2, ... (rather than 0, 4, 8, ...). This makes the design slightly simpler: you don't need a "shift left 2" circuit, and you add 1 (rather than 4) to the PC on each cycle.
You will design this Module by extending the DataPath module you created for Assignment 4. You may use either your own ALU or the ALU primitive provided for Assignment 4. The data memory component of the DataPath module should be given the component name "dmemory", and the instruction memory should be given the component name "imemory" within the CPU module.
We will test your module by storing some instructions into imemory, starting at address 0, storing some data into dmemory, and running your 'machine' for some clock cycles, and then seeing if the correct results apear in dmemory.
As for assignment 4, you are required to code and submit at least one (4 cycle) test, which corresponds to the sequence of instructions
This test adds the contents of locations 1 and 2 of main memory and stores the result in location 3. Please code this test as (static) method test (with no arguments) of class Asgn5Test. (Note that this method is much simpler than the corresponding one for assignment 4: here, you just initialize the imemory and toggle the clock a few times.)lw 16,1
You should send email to email@example.com which contains a single attachment containing the definitions of the DataPath class, the Asgn4Test class, and any other classes you needed to define DataPath. The subject line of the message should be "Assignment 5". It will be easier for me if the attachment file name is yourname.java.
We will test your submission in two ways: by running our own tests on the CPU, and by initializing memory locations 1 and 2, running your test method, and examining memory location 3.
This assignment is due April 22nd, and is worth 9 points towards your final grade. There is a penalty of 1/2 point for each school day the assignment is late.
Simulator for Assignment 5: This is a minor upgrade of the simulator, adding a read-only memory primitive. Upgrade documentation. Java code (release 4.0).
Implementing the control units:
The CPU requires two control units: a main control unit and an ALU control unit. For the ALU control unit, P&H provide a fairly simple, 5-gate solution shown in Figure C.3. For the main control unit, the solution, shown in Figure C.5, is somewhat more complex. You may take this approach, but an alternative which is easier to extend to additional opcodes is to use a ROM to directly encode the table in Figure C.4. That is, you would create a 64-word by 9-bit ROM, where word i of this memory contains the control signals for opcode i. For example, word 0 would hold "100100010" and word 35 would hold "011110000".
// create and initialize microinstruction ROMThis would be a simple example of a "microprogram memory".
Bus microOp = ib("microOp",9);
ROM rom = new ROM (microOp, opcode);
etc. (one line for each instruction)
addComponent ("ROM", rom);
// define fields of microinstruction
Wire RegDst = microOp.elem(8);
Wire ALUSrc = microOp.elem(7);
Wire MemtoReg = microOp.elem(6);
Wire RegWrite = microOp.elem(5);
Wire MemRead = microOp.elem(4); // not really needed for our CPU
Wire MemWrite = microOp.elem(3);
Wire Branch = microOp.elem(2);
Bus ALUOp = microOp.elem(0,2);