V22.0436 - Computer Architecture - Fall 1997 - Prof. Grishman

Course Schedule

last updated December 10, 1997

Class Date Topic Text Assignment
1 Sept. 3 Historical Perspective Chap. 1
Logic Design Appendix B
2 Sept. 8 Gates, TTs, & logic eqns B.2
3 Sept. 10 Canonical forms; prop. delay B.3 #1 (universality)
4 Sept. 15 Fan-in; Simulation
5 Sept. 17 FFs; Synchronous circuits B.4, B.5 #2 (comb. ckt.)
6 Sept. 22 Registers and RAMs B.5
7 Sept. 24 Finite-state machines B.6
Arithmetic Chap. 4
8 Sept. 29 MIPS Chap 3; 4.1-4.4 #3 (FSM)
9 Oct. 1 binary arith; MIPS ALU 4.5
10 Oct. 6 CLA #4 (MIPS)
Processor Design Chap. 5
11 Oct. 8 Building a data path 5.2
12 Oct. 13 Data paths/single cycle control 5.2, 5.3 #5 (ALU)
13 Oct. 15 Review for Mid-term
14 Oct. 20 Mid-term
15 Oct. 22 Multipliers 4.6
16 Oct. 27 (go over mid-term)
17 Oct. 29 MIPS: single cycle control 5.3 #6 (CPU)
Performance Issues
18 Nov. 3 measuring performance Chap. 2*
19 Nov. 5 multiple cycle control 5.4
20 Nov. 10 pipelining; memory technology 6.1-6.2*
Memory Chap. 7
21 Nov. 12 memory; cache 7.2 #7 (performance)
22 Nov. 17 cache 7.2
23 Nov. 19 cache; virtual memory 7.3
Input-output Chap. 8
24 Nov. 24 types of devices 8.2, 8.3
25 Nov. 26 buses 8.4 #8 (cache)
26 Dec. 1 DMA 8.5
27 Dec. 3 Real Busses
28 Dec. 8 Review for final exam    
29  Dec. 10 Review for final exam    

* partial coverage

Final exam, Dec. 17, 10:00 - 11:50, 109 WWH