### V22.0436 - Prof. Grishman

### Lecture 6: Logic Design -- Synchronous Circuits

#### Master-slave flip-flops

- provide an way of implementing edge-triggered FFs
- built from two simple flip-flops (latches) with complementary clocks

(text, figure B.15, page B-24)
- changes output on falling edge

#### Timing for synchronous circuits

- basic requirement: delay of combinational circuit to compute next state
< clock period (text, figure B.30, page B-40)

#### Representing sequential circuits

- a sequential circuit can be described as a
*finite state machine*

(text, section B.6)
- state machine includes a next-state function and an output function

(text, figure B.27)
- next-state function can be represented by a graph or a table
- graph: finite state transition network
- transition table: table which gives new state as a function of current
state and inputs